Add hulk.volatile
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@ -3,12 +3,12 @@
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*/
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module hulk.time;
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import core.volatile;
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import hulk.volatile;
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struct Time
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{
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/** System uptime (ms). */
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private static __gshared ulong s_uptime;
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private static __gshared Volatile!ulong s_uptime;
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/**
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* Millisecond ISR.
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@ -23,7 +23,7 @@ struct Time
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*/
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public static @property ulong uptime()
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{
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return volatileLoad(&s_uptime);
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return s_uptime;
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}
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/**
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@ -12,7 +12,7 @@ import hulk.pci;
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import hulk.hurl.a1;
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import hulk.klog;
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import hulk.time;
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import core.volatile;
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import hulk.volatile;
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struct XHCI
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{
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@ -27,14 +27,14 @@ struct XHCI
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* Offset from beginning of capability registers to beginning of
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* operational registers.
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*/
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ubyte capability_length;
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Volatile!ubyte capability_length;
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ubyte _reserved01;
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/**
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* Interface version number supported (psuedo-BSD).
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*/
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ushort hci_version;
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Volatile!ushort hci_version;
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/**
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* HCSPARAMS1.
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@ -43,7 +43,7 @@ struct XHCI
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* 23:19 reserved
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* 31:24 number of ports (MaxPorts)
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*/
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uint hcs_params1;
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Volatile!uint hcs_params1;
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/**
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* 3:0 isochronous scheduling threshold (IST)
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@ -53,14 +53,14 @@ struct XHCI
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* 26 scratchpad restore (SPR)
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* 31:27 max scratchpad buffers (low 5 bits)
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*/
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uint hcs_params2;
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Volatile!uint hcs_params2;
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/**
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* 7:0 U1 device exit latency
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* 15:8 reserved
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* 31:16 U2 device exit latency
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*/
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uint hcs_params3;
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Volatile!uint hcs_params3;
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/**
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* 0 64-bit addressing capability (AC64)
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@ -80,7 +80,7 @@ struct XHCI
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* offset in 32-bit words from base of capability registers to base
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* of capabilities list
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*/
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uint hcc_params1;
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Volatile!uint hcc_params1;
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/**
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* 1:0 reserved
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@ -88,13 +88,13 @@ struct XHCI
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* offset in 32-bit words from base of capability registers to the
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* doorbell array
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*/
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uint doorbell_offset;
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Volatile!uint doorbell_offset;
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/**
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* 4:0 reserved
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* 31:5 runtime register space offset
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*/
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uint rts_offset;
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Volatile!uint rts_offset;
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/**
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* 0 U3 entry capability (U3C)
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@ -109,13 +109,13 @@ struct XHCI
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* 9 virtualization based trusted I/O capability (VTC; xHCI v1.2+)
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* 31:10 reserved
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*/
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uint hcc_params2;
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Volatile!uint hcc_params2;
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/**
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* 11:0 reserved
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* 31:12 VTIO register space offset (xHCI v1.2+)
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*/
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uint vtios_offset;
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Volatile!uint vtios_offset;
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}
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static assert(CapabilityRegisters.sizeof == 0x24u);
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@ -142,7 +142,7 @@ struct XHCI
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* 16 VTIO enable (VTIOE; xHCI v1.2+)
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* 31:17 reserved
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*/
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uint usb_command;
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Volatile!uint usb_command;
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/**
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* 0 HCHalted
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@ -158,13 +158,13 @@ struct XHCI
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* 12 Host Controller Error (HCE)
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* 31:13 reserved
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*/
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uint usb_status;
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Volatile!uint usb_status;
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/**
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* 15:0 Page Size (actual page size is 2^(x+12))
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* 31:16 reserved
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*/
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uint page_size;
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Volatile!uint page_size;
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uint[2] _reserved01;
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@ -172,7 +172,7 @@ struct XHCI
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* 15:0 Notification Enable
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* 31:16 reserved
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*/
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uint dn_ctrl;
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Volatile!uint dn_ctrl;
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/**
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* 0 Ring Cycle State (RCS)
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@ -182,7 +182,7 @@ struct XHCI
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* 5:4 reserved
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* 63:6 Command Ring Pointer
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*/
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ulong cr_ctrl;
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Volatile!ulong cr_ctrl;
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uint[4] _reserved02;
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@ -190,7 +190,7 @@ struct XHCI
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* 5:0 reserved
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* 63:6 Device Context Base Address Array Pointer
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*/
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ulong dcbaap;
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Volatile!ulong dcbaap;
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/**
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* 7:0 Max Device Slots Enabled (MaxSlotsEn)
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@ -198,7 +198,7 @@ struct XHCI
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* 9 Configuration Information Enable (CIE; xHCI v1.1+)
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* 31:10 reserved
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*/
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uint config;
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Volatile!uint config;
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uint _reserved03;
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}
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@ -239,22 +239,22 @@ struct XHCI
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* 30 Device Removable
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* 31 Warm Port Reset
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*/
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uint portsc;
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Volatile!uint portsc;
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/**
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* Port Power Management Status and Control
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*/
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uint portpmsc;
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Volatile!uint portpmsc;
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/**
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* Port Link Info
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*/
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uint portli;
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Volatile!uint portli;
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/**
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* Port Hardware LPM Control (xHCI v1.1+)
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*/
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uint porthlpmc;
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Volatile!uint porthlpmc;
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}
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static assert(PortRegisters.sizeof == 0x10u);
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@ -266,7 +266,7 @@ struct XHCI
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/**
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* Microframe index. Incremented by controller each microframe.
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*/
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uint mfindex;
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Volatile!uint mfindex;
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uint[7] _reserved01;
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@ -289,21 +289,21 @@ struct XHCI
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* 1 Interrupt Enable
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* 31:2 reserved
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*/
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uint imr;
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Volatile!uint imr;
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/**
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* Interrupter Moderation.
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* 15:0 Interrupt Moderation Interval
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* 31:16 Interrupt Moderation Counter
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*/
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uint im;
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Volatile!uint im;
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/**
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* Event Ring Segment Table Size.
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* 15:0 Event Ring Segment Table Size
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* 31:16 reserved
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*/
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uint ersts;
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Volatile!uint ersts;
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uint reserved;
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@ -312,7 +312,7 @@ struct XHCI
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* 5:0 reserved
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* 63:6 Event Ring Segment Table Base Address
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*/
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ulong erstba;
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Volatile!ulong erstba;
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/**
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* Event Ring Dequeue Pointer.
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@ -320,7 +320,7 @@ struct XHCI
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* 3 Event Handler Busy
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* 63:4 Event Ring Dequeue Pointer
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*/
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ulong erdp;
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Volatile!ulong erdp;
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}
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/**
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@ -331,9 +331,9 @@ struct XHCI
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*/
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struct DoorbellRegister
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{
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ubyte target;
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Volatile!ubyte target;
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ubyte _reserved01;
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ushort task_id;
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Volatile!ushort task_id;
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}
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static assert(DoorbellRegister.sizeof == 4u);
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@ -361,7 +361,7 @@ struct XHCI
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/* TODO: write dcbaap. */
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/* TODO: write cr_ctrl. */
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/+ TODO:
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m_operational_registers.config = volatileLoad(&m_capability_registers.hcs_params1) & 0xFu;
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m_operational_registers.config = m_capability_registers.hcs_params1 & 0xFu;
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m_operational_registers.dn_ctrl = 1u << 1u;
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+/
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/* TODO: set up interrupt register set. */
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@ -419,7 +419,7 @@ struct XHCI
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{
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Time.msleep(1u);
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if ((volatileLoad(&m_operational_registers.usb_status) & 1u) != 0u)
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if ((m_operational_registers.usb_status & 1u) != 0u)
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{
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break;
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}
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@ -441,8 +441,8 @@ struct XHCI
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{
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Time.msleep(1u);
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if (((volatileLoad(&m_operational_registers.usb_command) & (1u << 1u)) == 0u) &&
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((volatileLoad(&m_operational_registers.usb_status) & (1u << 11u)) == 0u))
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if (((m_operational_registers.usb_command & (1u << 1u)) == 0u) &&
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((m_operational_registers.usb_status & (1u << 11u)) == 0u))
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{
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break;
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}
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35
src/hulk/volatile.d
Normal file
35
src/hulk/volatile.d
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@ -0,0 +1,35 @@
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module hulk.volatile;
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import core.volatile;
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struct Volatile(T)
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{
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private T value;
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public @property T read()
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{
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return volatileLoad(&value);
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}
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alias read this;
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public void opAssign(T value)
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{
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volatileStore(&this.value, value);
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}
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public T opUnary(string s)()
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{
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T v = read();
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mixin(s ~ "v;");
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volatileStore(&this.value, v);
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return v;
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}
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public T opOpAssign(string s)(T rhs)
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{
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T v = read();
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mixin("v " ~ s ~ "= rhs;");
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volatileStore(&this.value, v);
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return v;
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}
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}
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