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josh committed 2017-07-25 22:23:50 -04:00
1 parent e1682a2fe7
commit 345ef6c9f3
35 files changed
+804 -89
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kernel/sys/io.h
+26 -7
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@@ -13,25 +13,44 @@
//inline unsigned char inportb(unsigned short port);
//Writes a byte out to a port
static inline void outportb(unsigned int port, unsigned char value) // Output a byte to a port
static inline void outportb(unsigned int port, unsigned int value) // Output a byte to a port
{
asm volatile ("outb %%al,%%dx"::"d" (port), "a" (value));
asm volatile ("outb %%al,%%dx"::"d" (port), "a" (value));
}
//Writes a word out to a port
static inline void outportw(unsigned int port, unsigned int value) // Output a word to a port
{
asm volatile ("outw %%ax,%%dx"::"d" (port), "a" (value));
asm volatile ("outw %%ax,%%dx"::"d" (port), "a" (value));
}
//Writes a dword out to a port
static inline void outportd(unsigned int port, unsigned int value) // Output a word to a port
{
asm volatile ("outl %%eax,%%dx"::"d" (port), "a" (value));
}
//Reads a byte from a port
static inline unsigned char inportb(unsigned short port)
static inline unsigned char inportb(unsigned int port)
{
unsigned char ret_val;
asm volatile("inb %w1,%b0" : "=a"(ret_val) : "d"(port));
return ret_val;
}
asm volatile("inb %w1,%b0"
: "=a"(ret_val)
: "d"(port));
//Reads a word from a port
static inline unsigned short inportw(unsigned int port)
{
unsigned int ret_val;
asm volatile("inw %w1,%w0" : "=a"(ret_val) : "d"(port));
return ret_val;
}
//Reads a dword from a port
static inline unsigned int inportd(unsigned int port)
{
unsigned int ret_val;
asm volatile("inl %w1,%0" : "=a"(ret_val) : "d"(port));
return ret_val;
}
kernel/sys/pci.cpp
+61
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@@ -0,0 +1,61 @@
// pci.cpp
// Author: Josh Holtrop
// Date: 07/13/05
// Modified: 07/17/05
#define _HOS_CPP_
extern "C" {
#include "hos_defines.h"
#include "display/kout.h"
#include "sys/io.h"
}
#include "pci.h"
#include "lang/vector.h"
vector<pci_header_t> *pci_devices;
int pci_init()
{
pci_devices = new vector<pci_header_t>;
pci_scanBus(0);
return 0;
}
void pci_scanBus(u32_t bus)
{
pci_header_t pciHdr;
u32_t dev, func, off, reg, numFuncs;
for (dev = 0; dev < 32; dev++)
{
numFuncs = 1;
for (func = 0; func < 8; func++)
{
reg = pci_readConfigRegister(bus, dev, func, 0);
if (reg != 0 && reg != 0xFFFFFFFF)
{
for (off = 0; off < 0x40; off += 4)
*((u32_t *)(((u32_t)&pciHdr)+off)) = pci_readConfigRegister(bus, dev, func, off);
pci_devices->add(pciHdr);
if (func == 0 && (pciHdr.header & 0x80))
numFuncs = 8;
kprintf("PCI device %d.%d.%d:\t(%s)\n", bus, dev, func, pci_getDeviceClass(pciHdr.cls, pciHdr.subclass, pciHdr.progif));
if ((pciHdr.header & 0x7F) == 1)
pci_scanBus(pciHdr.h1_bus1);
}
}
}
}
u32_t pci_readConfigRegister(u32_t bus, u32_t dev, u32_t func, u32_t offset)
{
outportd(PCI_CONFIG_ADDRESS,
0x80000000 |
((bus & 0xFF) << 16) |
((dev & 0x1F) << 11) |
((func & 0x7) << 8) |
(offset & 0xFC));
return inportd(PCI_CONFIG_DATA);
}
kernel/sys/pci.h
+75
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@@ -0,0 +1,75 @@
// pci.h
// Author: Josh Holtrop
// Date: 07/13/05
// Modified: 07/13/05
#ifndef __HOS_PCI__
#define __HOS_PCI__ __HOS_PCI__
#define PCI_CONFIG_ADDRESS 0xCF8
#define PCI_CONFIG_DATA 0xCFC
#define PCI_HEADER_MF_MASK 0x80
#include "hos_defines.h"
typedef struct
{
u8_t subclass;
u8_t progif;
char *desc;
} pci_class_t;
typedef struct
{
u16_t vendorID; /* 0x00 Vender ID Number */
u16_t deviceID; /* 0x02 Device ID Number */
u16_t command; /* 0x04 Command Register */
u16_t status; /* 0x06 Status Register */
u8_t revision; /* 0x08 Revision ID */
u8_t progif; /* 0x09 Programming Interface */
u8_t subclass; /* 0x0A Subclass Number */
u8_t cls; /* 0x0B PCI Device Class */
u8_t cacheLineSize; /* 0x0C Cache Line Size (for DMA) */
u8_t latency; /* 0x0D Latency Timer (PCI Bus cycles) */
u8_t header; /* 0x0E bit7:multifunc, 0-6: header format */
u8_t bist; /* 0x0F Built-In Self Test Result */
/* Header-specific fields */
u32_t bar0; /* 0x10 */
u32_t bar1; /* 0x14 */
union { /* 0x18 */
u32_t bar2;
struct {
u8_t h1_bus0;
u8_t h1_bus1;
u8_t h1_secBus;
u8_t h1_secLatency;
};
};
u32_t bar3; /* 0x1C */
u32_t bar4; /* 0x20 */
u32_t bar5; /* 0x24 */
u32_t cardbusCIS; /* 0x28 ro */
u16_t ssVendorID; /* 0x2C */
u16_t ssID; /* 0x2E */
u32_t expansionAddr; /* 0x30 */
u32_t reserved[2]; /* 0x34 */
u8_t irq; /* 0x3C IRQ Number, 0 if none */
u8_t intPin; /* 0x3D Interrupt Pin, 0 if none, ro */
u8_t minGrant; /* 0x3E 250ns units, ro */
u8_t maxLatency; /* 0x3F 250ns units, ro */
} pci_header_t;
#ifdef _HOS_CPP_
extern "C" {
#endif
int pci_init();
u32_t pci_readConfigRegister(u32_t bus, u32_t dev, u32_t func, u32_t offset);
char *pci_getDeviceClass(u8_t cls, u8_t sub, u8_t progif);
void pci_scanBus(u32_t bus);
#ifdef _HOS_CPP_
}
#endif
#endif
kernel/sys/pci_classes.c
+112
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@@ -0,0 +1,112 @@
// pci_classes.c
// Author: Josh Holtrop
// Date: 07/21/05
// Modified: 07/21/05
// Had to be a C file because g++ doesn't like pci_classes declaration
#include "hos_defines.h"
#include "pci.h"
pci_class_t* pci_classes[] =
{
(pci_class_t[]) {
{1, 1, "Generic PCI VGA Device"},
{0xFF, 0xFF, "Generic PCI Device"}
},
(pci_class_t[]) {
{0, 0, "SCSI Controller"},
{1, 0xFF, "IDE Controller"},
{2, 0, "Floppy Disk Controller"},
{3, 0, "IPI Controller"},
{4, 0, "RAID Controller"},
{0xFF, 0xFF, "Generic Mass Storage Controller"}
},
(pci_class_t[]) {
{0, 0, "Ethernet Controller"},
{1, 0, "Token Ring Network Controller"},
{2, 0, "FDDI Controller"},
{3, 0, "ATM Controller"},
{0xFF, 0xFF, "Generic Network Controller"}
},
(pci_class_t[]) {
{0, 0, "VGA Compatible Controller"},
{0, 1, "8514 Compatible Display Controller"},
{1, 0, "XGA Controller"},
{0xFF, 0xFF, "Generic Display Controller"}
},
(pci_class_t[]) {
{0, 0, "Multimedia Video Device"},
{0, 0, "Multimedia Audio Device"},
{0xFF, 0xFF, "Generic Multimedia Device"}
},
(pci_class_t[]) {
{0, 0, "RAM Controller"},
{1, 0, "Flash Memory Controller"},
{0xFF, 0xFF, "Generic Memory Controller"}
},
(pci_class_t[]) {
{0, 0, "Host/PCI Bridge"},
{1, 0, "PCI/ISA Bridge"},
{2, 0, "PCI/EISA Bridge"},
{3, 0, "PCI/Micro Channel Bridge"},
{4, 0, "PCI/PCI Bridge"},
{5, 0, "PCI/PCMCIA Bridge"},
{6, 0, "PCI/NuBus Bridge"},
{7, 0, "PCI/CardBus Bridge"},
{0xFF, 0xFF, "Generic Bridge"}
},
(pci_class_t[]) {
{0, 0xFF, "Serial Controller"},
{1, 0xFF, "Parallel Port"},
{0xFF, 0xFF, "Generic Communications Device"}
},
(pci_class_t[]) {
{0, 0xFF, "Programmable Interrupt Controller"},
{1, 0xFF, "DMA Controller"},
{2, 0xFF, "System Timer"},
{3, 0xFF, "RTC Controller"},
{0xFF, 0xFF, "Generic System Peripheral"}
},
(pci_class_t[]) {
{0, 0, "Keyboard Controller"},
{1, 0, "Digitizer (Pen)"},
{2, 0, "Mouse Controller"},
{0xFF, 0xFF, ""}
},
(pci_class_t[]) {
{0xFF, 0xFF, "Docking Station"}
},
(pci_class_t[]) {
{0, 0, "386 Processor"},
{1, 0, "486 Processor"},
{2, 0, "Pentium Processor"},
{0x10, 0, "Alpha Processor"},
{0x20, 0, "PowerPC Processor"},
{0x40, 0, "Co-Processor"},
{0xFF, 0xFF, "Generic Processor"}
},
(pci_class_t[]) {
{0, 0, "Firewire (IEEE 1394) Controller"},
{1, 0, "ACCESS Bus Controller"},
{2, 0, "SSA (Serial Storage Architecture) Controller"},
{3, 0, "USB Controller"},
{0xFF, 0xFF, "Generic Serial Bus Controller"}
}
};
char *pci_getDeviceClass(u8_t cls, u8_t sub, u8_t progif)
{
if (cls < sizeof(pci_classes)/sizeof(pci_class_t *))
{
pci_class_t *pcls = pci_classes[cls];
for (;;)
{
if ( (pcls->subclass == 0xFF || pcls->subclass == sub)
&& (pcls->progif == 0xFF || pcls->progif == progif) )
return pcls->desc;
pcls++;
}
}
return "Unknown PCI Device";
}