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Route I/O APIC interrupts, enable RTC tick interrupt

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josh committed 2022-12-16 00:32:49 -05:00
1 parent 9adc248225
commit 4081a220ef
2 files changed
+64 -16
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src/hulk/idt.d
+26 -10
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@@ -12,9 +12,14 @@ import hulk.apic;
struct idt
{
public static enum ulong EXCEPTION_LAPIC_TIMER = 0x70u;
public static enum ulong EXCEPTION_LAPIC_LINT0 = 0x71u;
public static enum ulong EXCEPTION_LAPIC_LINT1 = 0x72u;
/* The I/O APIC is configured to map IRQ 0 to interrupt 64 (0x40). */
public static enum ulong INT_APIC_BASE = 0x40u; /* IRQ 0 */
public static enum ulong INT_APIC_COUNT = 24u;
public static enum ulong INT_APIC_TIMER = 0x70u;
public static enum ulong INT_APIC_LINT0 = 0x71u;
public static enum ulong INT_APIC_LINT1 = 0x72u;
public static enum ulong INT_APIC_SPURIOUS = 0xFFu;
struct idtr_t
{
@@ -99,19 +104,30 @@ struct idt
public extern(C) void isr(ulong vector, ulong arg)
{
if ((idt.EXCEPTION_LAPIC_TIMER <= vector) && (vector <= idt.EXCEPTION_LAPIC_LINT1))
if ((vector >= idt.INT_APIC_BASE) && (vector < (idt.INT_APIC_BASE + idt.INT_APIC_COUNT)))
{
apic.isr(vector);
}
else
{
console.clear();
fb.clear(0xFF8000u);
klog.writefln("ISR %u, 0x%x", vector, arg);
__asm("cli", "");
for (;;)
switch (vector)
{
__asm("hlt", "");
case idt.INT_APIC_TIMER:
case idt.INT_APIC_LINT0:
case idt.INT_APIC_LINT1:
case idt.INT_APIC_SPURIOUS:
apic.isr(vector);
break;
default:
console.clear();
fb.clear(0xFF8000u);
klog.writefln("ISR %u, 0x%x", vector, arg);
__asm("cli", "");
for (;;)
{
__asm("hlt", "");
}
}
}
}