got interrupts working, added sys/{pic,timer,cpu} modules, ready to work on multitasking

git-svn-id: svn://anubis/hos/trunk@69 5b3e749e-e535-0410-8002-a9bb6afbdfca

kernel/sys/Makefile

@@ -0,0 +1,2 @@
+
+include $(HOS_TOPLEVEL)/subdir.mak

kernel/sys/cpu.h

@@ -0,0 +1,34 @@
+
+#ifndef CPU_H
+#define CPU_H
+
+#include "hos_types.h"
+
+static u32_t read_cr0()
+{
+    u32_t val;
+    __asm__ __volatile__ ("movl %%cr0, %0" : "=r" (val));
+    return val;
+}
+
+static u32_t read_cr2()
+{
+    u32_t val;
+    __asm__ __volatile__ ("movl %%cr2, %0" : "=r" (val));
+    return val;
+}
+
+static u32_t read_cr3()
+{
+    u32_t val;
+    __asm__ __volatile__ ("movl %%cr3, %0" : "=r" (val));
+    return val;
+}
+
+#define set_cr0(val) \
+    __asm__ __volatile__ ("movl %0, %%cr0" : : "r" (val));
+
+#define set_cr3(val) \
+    __asm__ __volatile__ ("movl %0, %%cr3" : : "r" (val));
+
+#endif

kernel/sys/pic.cc

@@ -0,0 +1,29 @@
+
+#include "pic.h"
+#include "portio.h"
+
+/*
+ * Re-maps the Programmable Interrupr Controllers
+ * so IRQ0->pic1 base address, IRG8->pic2 base address
+ */
+void pic_remap(u8_t base1, u8_t base2)
+{
+    u8_t    a1, a2;
+
+    a1 = inportb(PIC1_DATA);        /* 0x21 */
+    a2 = inportb(PIC2_DATA);        /* 0xA1 */
+
+    outportb(PIC1_COMMAND, ICW1_INIT+ICW1_ICW4); /* 0x20, 0x10+0x01 00010001b */
+    outportb(PIC2_COMMAND, ICW1_INIT+ICW1_ICW4); /* 0xA0, 0x10+0x01 00010001b */
+    outportb(PIC1_DATA, base1);     /* 0x21, pic1 */
+    outportb(PIC2_DATA, base2);     /* 0xA1, pic2 */
+    outportb(PIC1_DATA, 4);         /* 0x21, 0x04 00000100b */
+    outportb(PIC2_DATA, 2);         /* 0xA1, 0x02 00000010b */
+    outportb(PIC1_DATA, ICW4_8086); /* 0x21, 0x01 00000001b */
+    outportb(PIC2_DATA, ICW4_8086); /* 0xA1, 0x01 00000001b */
+
+    outportb(PIC1_DATA, a1);        /* 0x21 */
+    outportb(PIC2_DATA, a2);        /* 0xA1 */
+}
+
+

kernel/sys/pic.h

@@ -0,0 +1,46 @@
+
+#ifndef PIC_H
+#define PIC_H
+
+#include "hos_types.h"
+#include "portio.h"
+
+#define PIC1            0x20
+#define PIC2            0xA0
+#define PIC1_COMMAND    PIC1
+#define PIC1_DATA       (PIC1+1)
+#define PIC2_COMMAND    PIC2
+#define PIC2_DATA       (PIC2+1)
+#define PIC_EOI         0x20
+
+#define ICW1_ICW4       0x01            /* ICW4 (not) needed */
+#define ICW1_SINGLE     0x02            /* Single (cascade) mode */
+#define ICW1_INTERVAL4  0x04            /* Call address interval 4 (8) */
+#define ICW1_LEVEL      0x08            /* Level triggered (edge) mode */
+#define ICW1_INIT       0x10            /* Initialization - required! */
+
+#define ICW4_8086       0x01            /* 8086/88 (MCS-80/85) mode */
+#define ICW4_AUTO       0x02            /* Auto (normal) EOI */
+#define ICW4_BUF_SLAVE  0x08            /* Buffered mode/slave */
+#define ICW4_BUF_MASTER 0x0C            /* Buffered mode/master */
+#define ICW4_SFNM       0x10            /* Special fully nested (not) */
+
+void pic_remap(u8_t base1, u8_t base2);
+
+/* Masks interrupts on first Programmable Interrupt Controller */
+#define pic_mask1(mask) outportb(PIC1_DATA, mask) /* 0x21, maskfield *OCW1* */
+
+/* Masks interrupts on second Programmable Interrupt Controller */
+#define pic_mask2(mask) outportb(PIC2_DATA, mask) /* 0xA1, maskfield *OCW1* */
+
+/* Signals an End Of Interrupt signal to the first PIC */
+#define pic_eoi() outportb(0x20, 0x20)
+
+/* Signals an End Of Interrupt signal to both the second and first PIC unit */
+static inline void pic_eoi2()
+{
+        outportb(0xA0, 0x20);
+        outportb(0x20, 0x20);
+}
+
+#endif

kernel/sys/timer.cc

@@ -0,0 +1,12 @@
+
+#include "timer.h"
+#include "portio.h"
+
+void timer_init(u32_t freq)
+{
+    /* how many ticks the PIT must wait before issuing an interrupt */
+    u32_t wait = 1193180 / freq;
+    outportb(0x43, 0x34);
+    outportb(0x40, wait);       /* LSB */
+    outportb(0x40, wait >> 8);  /* MSB */
+}

kernel/sys/timer.h

@@ -0,0 +1,9 @@
+
+#ifndef TIMER_H
+#define TIMER_H
+
+#include "hos_types.h"
+
+void timer_init(u32_t freq);
+
+#endif