Add struct definitions for all PCI header types
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src/hulk/pci.d
157
src/hulk/pci.d
@ -220,32 +220,153 @@ struct Pci
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struct Header
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static struct Configuration
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{
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{
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ushort vendor_id;
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static struct HeaderType0
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ushort device_id;
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{
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ushort command;
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ushort vendor_id;
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ushort status;
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ushort device_id;
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ubyte revision_id;
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ushort command;
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ubyte interface_id;
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ushort status;
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ubyte subclass_id;
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ubyte revision_id;
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ubyte class_id;
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ubyte interface_id;
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ubyte cache_line_size;
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ubyte subclass_id;
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ubyte latency_timer;
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ubyte class_id;
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ubyte header_type;
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ubyte cache_line_size;
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ubyte bist;
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ubyte latency_timer;
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ubyte header_type;
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ubyte bist;
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uint[6] base_addresses;
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uint cardbus_cis_pointer;
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ushort subsystem_vendor_id;
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ushort subsystem_id;
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uint expansion_rom_base_address;
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ubyte capabilities_pointer;
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ubyte[7] _reserved;
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ubyte interrupt_line;
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ubyte interrupt_pin;
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ubyte min_grant;
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ubyte max_latency;
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}
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/**
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* PCI configuration format for header type 1 (PCI-to-PCI bridge).
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*/
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static struct HeaderType1
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{
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ushort vendor_id;
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ushort device_id;
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ushort command;
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ushort status;
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ubyte revision_id;
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ubyte interface_id;
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ubyte subclass_id;
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ubyte class_id;
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ubyte cache_line_size;
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ubyte latency_timer;
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ubyte header_type;
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ubyte bist;
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uint[2] base_addresses;
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ubyte primary_bus_nr;
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ubyte secondary_bus_nr;
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ubyte subordinate_bus_nr;
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ubyte secondary_latency_timer;
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ubyte io_base;
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ubyte io_limit;
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ushort secondary_status;
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ushort memory_base;
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ushort memory_limit;
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ushort prefetchable_memory_base;
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ushort prefetchable_memory_limit;
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uint prefetchable_base_high;
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uint prefetchable_limit_high;
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ushort io_base_high;
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ushort io_limit_high;
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ubyte capability_pointer;
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ubyte[3] _reserved;
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uint expansion_rom_base_address;
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ubyte interrupt_line;
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ubyte interrupt_pin;
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ushort bridge_control;
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}
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/**
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* PCI configuration format for header type 2 (PCI-to-CardBus bridge).
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*/
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static struct HeaderType2
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{
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ushort vendor_id;
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ushort device_id;
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ushort command;
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ushort status;
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ubyte revision_id;
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ubyte interface_id;
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ubyte subclass_id;
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ubyte class_id;
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ubyte cache_line_size;
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ubyte latency_timer;
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ubyte header_type;
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ubyte bist;
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uint cardbus_base_address;
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ubyte capability_list_offset;
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ubyte _reserved;
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ushort secondary_status;
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ubyte pci_bus_nr;
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ubyte cardbus_bus_nr;
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ubyte subordinate_bus_nr;
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ubyte cardbus_latency_timer;
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uint base_address_0;
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uint memory_limit_0;
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uint base_address_1;
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uint memory_limit_1;
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uint io_base_address_0;
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uint io_limit_0;
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uint io_base_address_1;
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uint io_limit_1;
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ubyte interrupt_line;
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ubyte interrupt_pin;
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ushort bridge_control;
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ushort subsystem_device_id;
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ushort subsystem_vendor_id;
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uint legacy_base_address;
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}
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union
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{
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struct
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{
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ushort vendor_id;
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ushort device_id;
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ushort command;
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ushort status;
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ubyte revision_id;
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ubyte interface_id;
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ubyte subclass_id;
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ubyte class_id;
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ubyte cache_line_size;
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ubyte latency_timer;
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ubyte header_type;
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ubyte bist;
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}
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HeaderType0 header0;
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HeaderType1 header1;
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HeaderType2 header2;
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}
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}
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}
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private static void scan(ubyte bus_nr, ubyte device_nr, ubyte function_nr, ulong config_address)
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private static void scan(ubyte bus_nr, ubyte device_nr, ubyte function_nr, ulong config_address)
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{
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{
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Header * header = cast(Header *)config_address;
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Configuration * config = cast(Configuration *)config_address;
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if (header.vendor_id != 0xFFFFu)
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if (config.vendor_id != 0xFFFFu)
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{
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{
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Klog.writefln("Found PCI device %04x:%04x (%02x:%02x:%02x) at %02u:%02u.%u (%p)",
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Klog.writefln("Found PCI device %04x:%04x (%02x:%02x:%02x) at %02u:%02u.%u (%p)",
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header.vendor_id, header.device_id,
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config.vendor_id, config.device_id,
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header.class_id, header.subclass_id, header.interface_id,
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config.class_id, config.subclass_id, config.interface_id,
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bus_nr, device_nr, function_nr, config_address);
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bus_nr, device_nr, function_nr, config_address);
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if (function_nr == 0 && (header.header_type & 0x80u) != 0u)
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if (function_nr == 0 && (config.header_type & 0x80u) != 0u)
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{
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{
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for (function_nr = 1u; function_nr < MAX_FUNCTIONS_PER_DEVICE; function_nr++)
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for (function_nr = 1u; function_nr < MAX_FUNCTIONS_PER_DEVICE; function_nr++)
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{
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{
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