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4814b51daf
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cda45b205d
@ -16,105 +16,19 @@ struct XHCI
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{
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/**
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* Located at PCI base address.
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*
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* All are read-only.
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*/
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struct CapabilityRegisters
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{
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/**
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* Offset from beginning of capability registers to beginning of
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* operational registers.
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*/
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ubyte capability_length;
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ubyte _reserved01;
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/**
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* Interface version number supported (psuedo-BSD).
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*/
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ushort hci_version;
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/**
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* 7:0 number of device slots (MaxSlots)
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* 18:8 number of interrupters (MaxIntrs)
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* 23:19 reserved
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* 31:24 number of ports (MaxPorts)
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*/
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uint hcs_params1;
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/**
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* 3:0 isochronous scheduling threshold (IST)
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* 7:4 event ring segment table max (ERST Max)
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* 20:8 reserved
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* 25:21 max scratchpad buffers (high 5 bits; xHCI v1.1+)
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* 26 scratchpad restore (SPR)
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* 31:27 max scratchpad buffers (low 5 bits)
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*/
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uint hcs_params2;
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/**
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* 7:0 U1 device exit latency
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* 15:8 reserved
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* 31:16 U2 device exit latency
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*/
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uint hcs_params3;
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/**
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* 0 64-bit addressing capability (AC64)
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* 1 BW negotiation capability (BNC)
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* 2 context size (CSZ)
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* 3 port power control (PPC)
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* 4 port indicators (PIND)
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* 5 light HC reset capability (LHRC)
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* 6 latency tolerance messaging capability (LTC)
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* 7 no secondary SID support (NSS)
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* 8 parse all event data (PAE; xHCI v1.1+)
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* 9 stopped - short packet capability (SPC; xHCI v1.1+)
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* 10 stopped EDTLA capability (SEC; xHCI v1.1+)
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* 11 continuous frame ID capability (CFC; xHCI v1.1+)
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* 15:12 maximum primary stream array size (MaxPSASize)
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* 31:16 xHCI extended capabilities pointer (xECP)
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* offset in 32-bit words from base of capability registers to base
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* of capabilities list
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*/
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uint[3] hcs_params;
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uint hcc_params1;
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/**
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* 1:0 reserved
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* 31:2 doorbell array offset in 32-bit words
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* offset in 32-bit words from base of capability registers to the
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* doorbell array
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*/
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uint doorbell_offset;
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/**
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* 4:0 reserved
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* 31:5 runtime register space offset
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*/
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uint rts_offset;
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/**
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* 0 U3 entry capability (U3C)
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* 1 ConfigEP command max exit latency too large (CMC)
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* 2 force save context capability (FSC)
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* 3 compliance transition capability (CTC)
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* 4 large ESIT payload capability (LEC)
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* 5 configuration information capability (CIC)
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* 6 extended TBC capability (ETC)
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* 7 extended TBC TRB status capability (ETC_TSC)
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* 8 get/set extended property capability (GSC; xHCI v1.1+)
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* 9 virtualization based trusted I/O capability (VTC; xHCI v1.2+)
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* 31:10 reserved
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*/
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uint hcc_params2;
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/**
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* 11:0 reserved
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* 31:12 VTIO register space offset (xHCI v1.2+)
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*/
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uint vtios_offset;
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}
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static assert(CapabilityRegisters.sizeof == 0x24u);
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static assert(CapabilityRegisters.sizeof == 0x20u);
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/**
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* Located at offset capability_length from PCI base address.
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@ -177,47 +91,6 @@ struct XHCI
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m_port_registers = cast(PortRegisters *)(cast(void *)m_operational_registers + 0x400);
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m_runtime_registers = cast(RuntimeRegisters *)(base_address + m_capability_registers.rts_offset);
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m_doorbell_registers = cast(DoorbellRegister *)(base_address + m_capability_registers.doorbell_offset);
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dump_extended_capabilities();
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}
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private void dump_extended_capabilities()
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{
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size_t ext_cap_off = (m_capability_registers.hcc_params1 >> 16u);
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if (ext_cap_off != 0u)
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{
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Klog.writefln("Extended capabilities:");
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uint * extended_capabilities = cast(uint *)m_capability_registers + ext_cap_off;
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for (;;)
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{
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uint ec0 = extended_capabilities[0];
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size_t next_offset = (ec0 >> 8u) & 0xFFu;
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size_t len = next_offset;
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if (len < 1u)
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{
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len = 1u;
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}
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ubyte type = ec0 & 0xFFu;
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if (type == 2u)
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{
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len = 4u;
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}
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for (size_t i = 0u; i < len; i++)
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{
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uint ecv = extended_capabilities[i];
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Klog.writef(" %02X %02X %02X %02X",
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ecv & 0xFFu,
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(ecv >> 8u) & 0xFFu,
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(ecv >> 16u) & 0xFFu,
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(ecv >> 24u) & 0xFFu);
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}
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Klog.writef("\n");
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if (next_offset == 0u)
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{
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break;
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}
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extended_capabilities += next_offset;
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}
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}
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}
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static void build(Pci.Device * pci_device)
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