/**
 * eXtensible Host Controller Interface for Universal Serial Bus
 *
 * Documentation:
 * - https://wiki.osdev.org/EXtensible_Host_Controller_Interface
 * - https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf
 */

module hulk.usb.xhci;

import hulk.pci;
import hulk.hurl.a1;

struct XHCI
{
    /**
     * Located at PCI base address.
     */
    struct CapabilityRegisters
    {
        ubyte capability_length;
        ubyte _reserved01;
        ushort hci_version;
        uint[3] hcs_params;
        uint hcc_params1;
        uint doorbell_offset;
        uint rts_offset;
        uint hcc_params2;
    }
    static assert(CapabilityRegisters.sizeof == 0x20u);

    /**
     * Located at offset capability_length from PCI base address.
     */
    struct OperationalRegisters
    {
        uint usb_command;
        uint usb_status;
        uint page_size;
        uint[2] _reserved01;
        uint dn_ctrl;
        ulong cr_ctrl;
        uint[4] _reserved02;
        ulong dcbaap;
        uint config;
        uint _reserved03;
    }
    static assert(OperationalRegisters.sizeof == 0x40u);

    /**
     * Located at offset 0x400 from start of Operational Registers.
     */
    struct PortRegisters
    {
        uint portsc;
        uint portpmsc;
        uint portli;
        uint porthlpmc;
    }
    static assert(PortRegisters.sizeof == 0x10u);

    struct RuntimeRegisters
    {
        uint mfindex;
        uint[7] _reserved01;
        uint ir;
    }

    struct DoorbellRegister
    {
        ubyte target;
        ubyte _reserved01;
        ushort task_id;
    }
    static assert(DoorbellRegister.sizeof == 4u);

    void initialize(Pci.Device * pci_device)
    {
    }

    static void build(Pci.Device * pci_device)
    {
        if (pci_device.memory_ranges[0].address != null)
        {
            XHCI * xhci = A1.allocate!XHCI();
            xhci.initialize(pci_device);
        }
    }
}