// pci.h
// Author: Josh Holtrop
// Date: 07/13/05
// Modified: 07/13/05

#ifndef __HOS_PCI__
#define __HOS_PCI__ __HOS_PCI__

#define PCI_CONFIG_ADDRESS	0xCF8
#define PCI_CONFIG_DATA		0xCFC
#define PCI_HEADER_MF_MASK	0x80

#include "hos_defines.h"

typedef struct
{
	u8_t	subclass;
	u8_t	progif;
	char	*desc;
} pci_class_t;

typedef struct
{
	u16_t	vendorID;	/* 0x00 Vender ID Number */
	u16_t	deviceID;	/* 0x02 Device ID Number */
	u16_t	command;	/* 0x04 Command Register */
	u16_t	status;		/* 0x06 Status Register */
	u8_t	revision;	/* 0x08 Revision ID */
	u8_t	progif;		/* 0x09 Programming Interface */
	u8_t	subclass;	/* 0x0A Subclass Number */
	u8_t	cls;		/* 0x0B PCI Device Class */
	u8_t	cacheLineSize;	/* 0x0C Cache Line Size (for DMA) */
	u8_t	latency;	/* 0x0D Latency Timer (PCI Bus cycles) */
	u8_t	header;		/* 0x0E bit7:multifunc, 0-6: header format */
	u8_t	bist;		/* 0x0F Built-In Self Test Result */
  /* Header-specific fields */
	u32_t	bar0;		/* 0x10 */
	u32_t	bar1;		/* 0x14 */
	union {			/* 0x18 */
		u32_t	bar2;
		struct {
			u8_t	h1_bus0;
			u8_t	h1_bus1;
			u8_t	h1_secBus;
			u8_t	h1_secLatency;
		};
	};
	u32_t	bar3;		/* 0x1C */
	u32_t	bar4;		/* 0x20 */
	u32_t	bar5;		/* 0x24 */
	u32_t	cardbusCIS;	/* 0x28 ro */
	u16_t	ssVendorID;	/* 0x2C */
	u16_t	ssID;		/* 0x2E */
	u32_t	expansionAddr;	/* 0x30 */
	u32_t	reserved[2];	/* 0x34 */
	u8_t	irq;		/* 0x3C IRQ Number, 0 if none */
	u8_t	intPin;		/* 0x3D Interrupt Pin, 0 if none, ro */
	u8_t	minGrant;	/* 0x3E 250ns units, ro */
	u8_t	maxLatency;	/* 0x3F 250ns units, ro */
} pci_header_t;

#ifdef _HOS_CPP_
extern "C" {
#endif

int	pci_init();
u32_t	pci_readConfigRegister(u32_t bus, u32_t dev, u32_t func, u32_t offset);
char	*pci_getDeviceClass(u8_t cls, u8_t sub, u8_t progif);
  void	pci_scanBus(u32_t bus);

#ifdef _HOS_CPP_
}
#endif

#endif