76 lines
1.8 KiB
C
76 lines
1.8 KiB
C
// pci.h
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// Author: Josh Holtrop
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// Date: 07/13/05
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// Modified: 07/13/05
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#ifndef __HOS_PCI__
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#define __HOS_PCI__ __HOS_PCI__
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#define PCI_CONFIG_ADDRESS 0xCF8
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#define PCI_CONFIG_DATA 0xCFC
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#define PCI_HEADER_MF_MASK 0x80
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#include "hos_defines.h"
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typedef struct
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{
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u8_t subclass;
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u8_t progif;
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char *desc;
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} pci_class_t;
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typedef struct
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{
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u16_t vendorID; /* 0x00 Vender ID Number */
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u16_t deviceID; /* 0x02 Device ID Number */
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u16_t command; /* 0x04 Command Register */
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u16_t status; /* 0x06 Status Register */
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u8_t revision; /* 0x08 Revision ID */
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u8_t progif; /* 0x09 Programming Interface */
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u8_t subclass; /* 0x0A Subclass Number */
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u8_t cls; /* 0x0B PCI Device Class */
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u8_t cacheLineSize; /* 0x0C Cache Line Size (for DMA) */
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u8_t latency; /* 0x0D Latency Timer (PCI Bus cycles) */
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u8_t header; /* 0x0E bit7:multifunc, 0-6: header format */
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u8_t bist; /* 0x0F Built-In Self Test Result */
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/* Header-specific fields */
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u32_t bar0; /* 0x10 */
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u32_t bar1; /* 0x14 */
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union { /* 0x18 */
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u32_t bar2;
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struct {
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u8_t h1_bus0;
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u8_t h1_bus1;
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u8_t h1_secBus;
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u8_t h1_secLatency;
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};
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};
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u32_t bar3; /* 0x1C */
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u32_t bar4; /* 0x20 */
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u32_t bar5; /* 0x24 */
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u32_t cardbusCIS; /* 0x28 ro */
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u16_t ssVendorID; /* 0x2C */
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u16_t ssID; /* 0x2E */
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u32_t expansionAddr; /* 0x30 */
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u32_t reserved[2]; /* 0x34 */
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u8_t irq; /* 0x3C IRQ Number, 0 if none */
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u8_t intPin; /* 0x3D Interrupt Pin, 0 if none, ro */
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u8_t minGrant; /* 0x3E 250ns units, ro */
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u8_t maxLatency; /* 0x3F 250ns units, ro */
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} pci_header_t;
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#ifdef _HOS_CPP_
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extern "C" {
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#endif
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int pci_init();
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u32_t pci_readConfigRegister(u32_t bus, u32_t dev, u32_t func, u32_t offset);
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char *pci_getDeviceClass(u8_t cls, u8_t sub, u8_t progif);
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void pci_scanBus(u32_t bus);
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#ifdef _HOS_CPP_
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}
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#endif
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#endif
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