diff --git a/joshs_svga_controller/joshs_svga_controller.ise b/joshs_svga_controller/joshs_svga_controller.ise index ffef59d..f2a2aea 100644 Binary files a/joshs_svga_controller/joshs_svga_controller.ise and b/joshs_svga_controller/joshs_svga_controller.ise differ diff --git a/joshs_svga_controller/joshs_svga_controller.restore b/joshs_svga_controller/joshs_svga_controller.restore index 1a90f2f..94a13bf 100644 --- a/joshs_svga_controller/joshs_svga_controller.restore +++ b/joshs_svga_controller/joshs_svga_controller.restore @@ -835,13 +835,17 @@ proc restore { { project_dir "" } } { RestoreProjectSettings $iProjHelper $project_settings } "A problem occured while restoring project settings." - set user_files {} + set user_files { + "joshs_svga_controller.vhd" + "main.vhd" + "nexys2.ucf"} HandleException { AddUserFiles $iProjHelper $user_files } "A problem occured while restoring user files." - set imported_files {} + set imported_files { + "main_guide.ncd"} set origination 2 @@ -851,12 +855,13 @@ proc restore { { project_dir "" } } { set process_props { "A" "" "" "" "PROPEXT_SynthMultStyle_virtex2" "Auto" + "A" "" "" "" "PROPEXT_xilxBitgCfg_DCIUpdateMode_spartan3" "As Required" "A" "" "" "" "PROPEXT_xilxBitgCfg_Rate_spartan3e" "Default (1)" "A" "" "" "" "PROPEXT_xilxMapGenInputK_virtex2" "4" "A" "" "" "" "PROPEXT_xilxSynthAddBufg_spartan3e" "24" "A" "" "" "" "PROPEXT_xilxSynthMaxFanout_virtex2" "500" "A" "" "" "" "PROP_AutoGenFile" "false" - "A" "" "" "" "PROP_BehavioralSimTop" "" + "A" "" "" "" "PROP_BehavioralSimTop" "Architecture|main|Behavioral" "A" "" "" "" "PROP_CPLDFitkeepio" "false" "A" "" "" "" "PROP_CompxlibAbelLib" "true" "A" "" "" "" "PROP_CompxlibCPLDDetLib" "true" @@ -865,7 +870,11 @@ proc restore { { project_dir "" } } { "A" "" "" "" "PROP_CompxlibOverwriteLib" "Overwrite" "A" "" "" "" "PROP_CompxlibSimPrimatives" "true" "A" "" "" "" "PROP_CompxlibXlnxCoreLib" "true" + "A" "" "" "" "PROP_ConstFileAddOption" "true" + "A" "" "" "" "PROP_ConstFileName" "" + "A" "" "" "" "PROP_CorgenRegenCore" "Under Current Project Setting" "A" "" "" "" "PROP_CurrentFloorplanFile" "" + "A" "" "" "" "PROP_DefaultTBName" "Default" "A" "" "" "" "PROP_DesignName" "joshs_svga_controller" "A" "" "" "" "PROP_Dummy" "dum1" "A" "" "" "" "PROP_EnableWYSIWYG" "None" @@ -875,18 +884,31 @@ proc restore { { project_dir "" } } { "A" "" "" "" "PROP_FitterReportFormat" "HTML" "A" "" "" "" "PROP_FlowDebugLevel" "0" "A" "" "" "" "PROP_FunctionBlockInputLimit" "38" + "A" "" "" "" "PROP_HierarchicalProjectType" "N/A" "A" "" "" "" "PROP_ISimLibSearchOrderFile" "" "A" "" "" "" "PROP_ISimOtherCompilerOptions_behav" "" "A" "" "" "" "PROP_ISimOtherCompilerOptions_par" "" "A" "" "" "" "PROP_ISimSDFTimingToBeRead" "Setup Time" + "A" "" "" "" "PROP_ISimSpecifyDefMacroAndValueChkSyntax" "" + "A" "" "" "" "PROP_ISimSpecifySearchDirectoryChkSyntax" "" "A" "" "" "" "PROP_ISimUseCustomCompilationOrder" "false" "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_behav_tb" "false" "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_behav_tbw" "false" "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_gen_tbw" "false" + "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_launch" "false" "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_par_tb" "false" "A" "" "" "" "PROP_ISimUseCustomSimCmdFile_par_tbw" "false" "A" "" "" "" "PROP_ISimUutInstName" "UUT" "A" "" "" "" "PROP_ImpactProjectFile" "Default" + "A" "" "" "" "PROP_LastAppliedGoal" "Balanced" + "A" "" "" "" "PROP_LastAppliedStrategy" "Xilinx Default (unlocked)" + "A" "" "" "" "PROP_LastUnlockStatus" "false" + "A" "" "" "" "PROP_LoadPostTrceTSIFile" "false" + "A" "" "" "" "PROP_MSimSDFTimingToBeRead" "Setup Time" + "A" "" "" "" "PROP_MapGlobalOptimization" "false" + "A" "" "" "" "PROP_ModelSimUseConfigName" "false" + "A" "" "" "" "PROP_OverwriteSym" "false" + "A" "" "" "" "PROP_Parse_Edif_Module" "false" "A" "" "" "" "PROP_Parse_Target" "synthesis" "A" "" "" "" "PROP_PartitionCreateDelete" "" "A" "" "" "" "PROP_PartitionForcePlacement" "" @@ -894,41 +916,103 @@ proc restore { { project_dir "" } } { "A" "" "" "" "PROP_PartitionForceTranslate" "" "A" "" "" "" "PROP_PlsClockEnable" "true" "A" "" "" "" "PROP_PostFitSimTop" "" - "A" "" "" "" "PROP_PostMapSimTop" "" - "A" "" "" "" "PROP_PostParSimTop" "" - "A" "" "" "" "PROP_PostSynthSimTop" "" + "A" "" "" "" "PROP_PostMapSimTop" "Architecture|main|Behavioral" + "A" "" "" "" "PROP_PostParSimTop" "Architecture|main|Behavioral" + "A" "" "" "" "PROP_PostSynthSimTop" "Architecture|main|Behavioral" "A" "" "" "" "PROP_PostTrceFastPath" "false" "A" "" "" "" "PROP_PostTrceGenDatasheet" "true" "A" "" "" "" "PROP_PostTrceGenTimegroups" "false" - "A" "" "" "" "PROP_PostXlateSimTop" "" + "A" "" "" "" "PROP_PostXlateSimTop" "Architecture|main|Behavioral" "A" "" "" "" "PROP_PreTrceFastPath" "false" "A" "" "" "" "PROP_PreTrceGenDatasheet" "true" "A" "" "" "" "PROP_PreTrceGenTimegroups" "false" "A" "" "" "" "PROP_PreTrceTSIFile" "" + "A" "" "" "" "PROP_PrecAddIOPads" "true" + "A" "" "" "" "PROP_PrecAdvFsmOptimization" "true" + "A" "" "" "" "PROP_PrecArrayBoundsCheck" "false" + "A" "" "" "" "PROP_PrecCreateUcfFromRtlConstraints" "false" + "A" "" "" "" "PROP_PrecEdif" "true" + "A" "" "" "" "PROP_PrecFsmEncoding" "Auto" + "A" "" "" "" "PROP_PrecFullCase" "false" + "A" "" "" "" "PROP_PrecInputSdcFile" "" + "A" "" "" "" "PROP_PrecOutputFileBase" "" + "A" "" "" "" "PROP_PrecParallelCase" "false" + "A" "" "" "" "PROP_PrecResourceSharing" "true" + "A" "" "" "" "PROP_PrecRptCriticalPaths" "true" + "A" "" "" "" "PROP_PrecRptMissingConstraints" "false" + "A" "" "" "" "PROP_PrecRptTimingSummary" "true" + "A" "" "" "" "PROP_PrecRptTimingViolations" "true" + "A" "" "" "" "PROP_PrecRptclockFreq" "true" + "A" "" "" "" "PROP_PrecRunRetiming" "false" + "A" "" "" "" "PROP_PrecShowClockDomainCrossing" "false" + "A" "" "" "" "PROP_PrecShowNetFanOut" "true" + "A" "" "" "" "PROP_PrecTranSetResetToLatches" "true" + "A" "" "" "" "PROP_PrecUseSafeFsm" "false" + "A" "" "" "" "PROP_PrecVerilog" "false" + "A" "" "" "" "PROP_PrecVhdl" "false" + "A" "" "" "" "PROP_PrecVhdlSyntax" "VHDL 93" + "A" "" "" "" "PROP_ProjectGeneratorType" "ProjNav" + "A" "" "" "" "PROP_SimDo" "true" "A" "" "" "" "PROP_SimModelGenerateTestbenchFile" "false" "A" "" "" "" "PROP_SimModelInsertBuffersPulseSwallow" "false" "A" "" "" "" "PROP_SimModelOtherNetgenOpts" "" "A" "" "" "" "PROP_SimModelRetainHierarchy" "true" + "A" "" "" "" "PROP_SimUseCustom_behav" "false" + "A" "" "" "" "PROP_SimUseCustom_launchMSim" "false" + "A" "" "" "" "PROP_SimUseCustom_postMap" "false" + "A" "" "" "" "PROP_SimUseCustom_postPar" "false" + "A" "" "" "" "PROP_SimUseCustom_postXlate" "false" + "A" "" "" "" "PROP_SimUserCompileList_launchMSim" "" + "A" "" "" "" "PROP_StartImpView" "" + "A" "" "" "" "PROP_StopImpView" "AbstractSynthesis" "A" "" "" "" "PROP_SynthCaseImplStyle" "None" "A" "" "" "" "PROP_SynthDecoderExtract" "true" + "A" "" "" "" "PROP_SynthDisableIOInsertion" "false" "A" "" "" "" "PROP_SynthEncoderExtract" "Yes" + "A" "" "" "" "PROP_SynthEnumEncoding" "default" "A" "" "" "" "PROP_SynthExtractMux" "Yes" "A" "" "" "" "PROP_SynthExtractRAM" "true" "A" "" "" "" "PROP_SynthExtractROM" "true" + "A" "" "" "" "PROP_SynthFanout" "100" "A" "" "" "" "PROP_SynthFsmEncode" "Auto" "A" "" "" "" "PROP_SynthLogicalShifterExtract" "true" + "A" "" "" "" "PROP_SynthModular" "false" + "A" "" "" "" "PROP_SynthNumCriticalPaths" "0" + "A" "" "" "" "PROP_SynthNumStartEndPoints" "0" "A" "" "" "" "PROP_SynthOpt" "Speed" "A" "" "" "" "PROP_SynthOptEffort" "Normal" + "A" "" "" "" "PROP_SynthPipelining" "true" + "A" "" "" "" "PROP_SynthProcBound" "true" "A" "" "" "" "PROP_SynthResSharing" "true" + "A" "" "" "" "PROP_SynthResourceSharing" "true" + "A" "" "" "" "PROP_SynthRetiming" "false" "A" "" "" "" "PROP_SynthShiftRegExtract" "true" - "A" "" "" "" "PROP_SynthTop" "" + "A" "" "" "" "PROP_SynthSymbolicFsm" "true" + "A" "" "" "" "PROP_SynthTop" "Architecture|main|Behavioral" + "A" "" "" "" "PROP_SynthUseFsmExplorerData" "false" "A" "" "" "" "PROP_SynthXORCollapse" "true" + "A" "" "" "" "PROP_ToolPathChipscope" "" + "A" "" "" "" "PROP_ToolPathLeonardoSpectrum" "" + "A" "" "" "" "PROP_ToolPathModelSim" "" + "A" "" "" "" "PROP_ToolPathPrecision" "" + "A" "" "" "" "PROP_ToolPathSynplify" "" + "A" "" "" "" "PROP_ToolPathSynplifyPro" "" "A" "" "" "" "PROP_Top_Level_Module_Type" "HDL" "A" "" "" "" "PROP_UseDataGate" "true" "A" "" "" "" "PROP_UseSmartGuide" "false" + "A" "" "" "" "PROP_UserBrowsedStrategyFiles" "" "A" "" "" "" "PROP_UserConstraintEditorPreference" "Constraints Editor" "A" "" "" "" "PROP_UserEditorCustomSetting" ""C:/Program Files/Vim/vim71/gvim.exe" --remote-tab-silent "$1"" "A" "" "" "" "PROP_UserEditorPreference" "Custom" + "A" "" "" "" "PROP_Verilog2001" "true" + "A" "" "" "" "PROP_VirtexSynthAutoConstrain" "true" + "A" "" "" "" "PROP_WriteVHDLNetlist" "false" + "A" "" "" "" "PROP_WriteVendorConstFile" "true" + "A" "" "" "" "PROP_WriteVerilogNetlist" "false" + "A" "" "" "" "PROP_XPORTInpFileName" "" + "A" "" "" "" "PROP_XPORTInpFileType" "ABEL" + "A" "" "" "" "PROP_XPORTOutFileType" "VHDL" + "A" "" "" "" "PROP_XPORTlistInpFiles" "false" "A" "" "" "" "PROP_XPowerOptInputTclScript" "" "A" "" "" "" "PROP_XPowerOptLoadPCFFile" "Default" "A" "" "" "" "PROP_XPowerOptLoadVCDFile" "Default" @@ -937,6 +1021,14 @@ proc restore { { project_dir "" } } { "A" "" "" "" "PROP_XPowerOptVerboseRpt" "false" "A" "" "" "" "PROP_XPowerOtherXPowerOpts" "" "A" "" "" "" "PROP_XplorerMode" "Off" + "A" "" "" "" "PROP_bitgen_Encrypt_keySeq0" "None" + "A" "" "" "" "PROP_bitgen_Encrypt_keySeq1" "None" + "A" "" "" "" "PROP_bitgen_Encrypt_keySeq2" "None" + "A" "" "" "" "PROP_bitgen_Encrypt_keySeq3" "None" + "A" "" "" "" "PROP_bitgen_Encrypt_keySeq4" "None" + "A" "" "" "" "PROP_bitgen_Encrypt_keySeq5" "None" + "A" "" "" "" "PROP_bitgen_Encrypt_startCBC" "" + "A" "" "" "" "PROP_bitgen_Encrypt_startKey" "None" "A" "" "" "" "PROP_bitgen_otherCmdLineOptions" "" "A" "" "" "" "PROP_cpldBestFit" "false" "A" "" "" "" "PROP_cpldfitHDLeqStyle" "Source" @@ -944,6 +1036,7 @@ proc restore { { project_dir "" } } { "A" "" "" "" "PROP_fitGenSimModel" "false" "A" "" "" "" "PROP_hprep6_autosig" "false" "A" "" "" "" "PROP_hprep6_otherCmdLineOptions" "" + "A" "" "" "" "PROP_ibiswriterGeneratePackageParasitics" "false" "A" "" "" "" "PROP_ibiswriterShowAllModels" "false" "A" "" "" "" "PROP_isimCompileForHdlDebug" "true" "A" "" "" "" "PROP_isimIncreCompilation" "true" @@ -952,12 +1045,16 @@ proc restore { { project_dir "" } } { "A" "" "" "" "PROP_isimValueRangeCheck" "false" "A" "" "" "" "PROP_lockPinsUcfFile" "" "A" "" "" "" "PROP_mapIgnoreTimingConstraints" "false" + "A" "" "" "" "PROP_mapTimingAnalyzerLoadDesign" "true" "A" "" "" "" "PROP_mapUseRLOCConstraints" "true" "A" "" "" "" "PROP_map_otherCmdLineOptions" "" "A" "" "" "" "PROP_mpprRsltToCopy" "" + "A" "" "" "" "PROP_mpprViewPadRptsForAllRslt" "true" + "A" "" "" "" "PROP_mpprViewParRptsForAllRslt" "true" "A" "" "" "" "PROP_ngdbuildUseLOCConstraints" "true" "A" "" "" "" "PROP_ngdbuild_otherCmdLineOptions" "" "A" "" "" "" "PROP_parIgnoreTimingConstraints" "false" + "A" "" "" "" "PROP_parTimingAnalyzerLoadDesign" "true" "A" "" "" "" "PROP_parUseTimingConstraints" "true" "A" "" "" "" "PROP_par_otherCmdLineOptions" "" "A" "" "" "" "PROP_primeCorrelateOutput" "false" @@ -965,6 +1062,7 @@ proc restore { { project_dir "" } } { "A" "" "" "" "PROP_primeTopLevelModule" "" "A" "" "" "" "PROP_primetimeBlockRamData" "" "A" "" "" "" "PROP_taengine_otherCmdLineOptions" "" + "A" "" "" "" "PROP_usedsp48" "Auto" "A" "" "" "" "PROP_xcpldFitDesInit" "Low" "A" "" "" "" "PROP_xcpldFitDesInputLmt_xbr" "32" "A" "" "" "" "PROP_xcpldFitDesMultiLogicOpt" "true" @@ -979,7 +1077,9 @@ proc restore { { project_dir "" } } { "A" "" "" "" "PROP_xcpldUseGlobalOutputEnables" "true" "A" "" "" "" "PROP_xcpldUseGlobalSetReset" "true" "A" "" "" "" "PROP_xcpldUseLocConst" "Always" + "A" "" "" "" "PROP_xilxBitgCfg_Clk" "Pull Up" "A" "" "" "" "PROP_xilxBitgCfg_Code" "0xFFFFFFFF" + "A" "" "" "" "PROP_xilxBitgCfg_DCMBandgap" "false" "A" "" "" "" "PROP_xilxBitgCfg_DCMShutdown" "false" "A" "" "" "" "PROP_xilxBitgCfg_Done" "Pull Up" "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ASCIIFile" "false" @@ -988,10 +1088,18 @@ proc restore { { project_dir "" } } { "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_Compress" "false" "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_DRC" "true" "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_EnableCRC" "true" + "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_GClkDel0" "11111" + "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_GClkDel1" "11111" + "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_GClkDel2" "11111" + "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_GClkDel3" "11111" "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_IEEE1532File" "false" "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_IEEE1532File_xbr" "false" "A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ReadBack" "false" + "A" "" "" "" "PROP_xilxBitgCfg_M0" "Pull Up" + "A" "" "" "" "PROP_xilxBitgCfg_M1" "Pull Up" + "A" "" "" "" "PROP_xilxBitgCfg_M2" "Pull Up" "A" "" "" "" "PROP_xilxBitgCfg_Pgm" "Pull Up" + "A" "" "" "" "PROP_xilxBitgCfg_PwrDown" "Pull Up" "A" "" "" "" "PROP_xilxBitgCfg_TCK" "Pull Up" "A" "" "" "" "PROP_xilxBitgCfg_TDI" "Pull Up" "A" "" "" "" "PROP_xilxBitgCfg_TDO" "Pull Up" @@ -1002,7 +1110,9 @@ proc restore { { project_dir "" } } { "A" "" "" "" "PROP_xilxBitgStart_Clk_Done" "Default (4)" "A" "" "" "" "PROP_xilxBitgStart_Clk_DriveDone" "false" "A" "" "" "" "PROP_xilxBitgStart_Clk_EnOut" "Default (5)" + "A" "" "" "" "PROP_xilxBitgStart_Clk_MatchCycle" "Auto" "A" "" "" "" "PROP_xilxBitgStart_Clk_RelDLL" "Default (NoWait)" + "A" "" "" "" "PROP_xilxBitgStart_Clk_RelSet" "Default (6)" "A" "" "" "" "PROP_xilxBitgStart_Clk_WrtEn" "Default (6)" "A" "" "" "" "PROP_xilxBitgStart_IntDone" "false" "A" "" "" "" "PROP_xilxMapAllowLogicOpt" "false" @@ -1045,6 +1155,7 @@ proc restore { { project_dir "" } } { "A" "" "" "" "PROP_xilxSynthRegBalancing" "No" "A" "" "" "" "PROP_xilxSynthRegDuplication" "true" "A" "" "" "" "PROP_xilxSynthXORPreserve" "true" + "A" "" "" "" "PROP_xilxTriStateBuffTXMode" "Off" "A" "" "" "" "PROP_xstAsynToSync" "false" "A" "" "" "" "PROP_xstAutoBRAMPacking" "false" "A" "" "" "" "PROP_xstBRAMUtilRatio" "100" @@ -1052,6 +1163,7 @@ proc restore { { project_dir "" } } { "A" "" "" "" "PROP_xstCase" "Maintain" "A" "" "" "" "PROP_xstCoresSearchDir" "" "A" "" "" "" "PROP_xstCrossClockAnalysis" "false" + "A" "" "" "" "PROP_xstDSPUtilRatio" "100" "A" "" "" "" "PROP_xstEquivRegRemoval" "true" "A" "" "" "" "PROP_xstFsmStyle" "LUT" "A" "" "" "" "PROP_xstGenerateRTLNetlist" "Yes" @@ -1065,6 +1177,7 @@ proc restore { { project_dir "" } } { "A" "" "" "" "PROP_xstReadCores" "true" "A" "" "" "" "PROP_xstSlicePacking" "true" "A" "" "" "" "PROP_xstSliceUtilRatio" "100" + "A" "" "" "" "PROP_xstTristate2Logic" "Yes" "A" "" "" "" "PROP_xstUseClockEnable" "Yes" "A" "" "" "" "PROP_xstUseSyncReset" "Yes" "A" "" "" "" "PROP_xstUseSyncSet" "Yes" @@ -1076,6 +1189,7 @@ proc restore { { project_dir "" } } { "A" "" "" "" "PROP_xstWorkDir" "./xst" "A" "" "" "" "PROP_xstWriteTimingConstraints" "false" "A" "" "" "" "PROP_xst_otherCmdLineOptions" "" + "A" "" "" "PROP_SteCreatedBy" "PROP_SteCreatedBy" "" "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimIncreCompilation" "true" "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" "" "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimSpecifySearchDirectory" "" @@ -1110,12 +1224,15 @@ proc restore { { project_dir "" } } { "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_XSTPreSynthesis" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_XSTPreSynthesis" "" "PROP_xstVeriIncludeDir" "" + "B" "" "" "" "PROPEXT_SynthFrequencySyn_virtex" "0.0" + "B" "" "" "" "PROP_AceActiveName" "" "B" "" "" "" "PROP_DevFamily" "Spartan3E" "B" "" "" "" "PROP_FitterOptimization_xpla3" "Density" "B" "" "" "" "PROP_ISimCustomCompilationOrderFile" "" "B" "" "" "" "PROP_ISimCustomSimCmdFileName_behav_tb" "" "B" "" "" "" "PROP_ISimCustomSimCmdFileName_behav_tbw" "" "B" "" "" "" "PROP_ISimCustomSimCmdFileName_gen_tbw" "" + "B" "" "" "" "PROP_ISimCustomSimCmdFileName_launch" "" "B" "" "" "" "PROP_ISimCustomSimCmdFileName_par_tb" "" "B" "" "" "" "PROP_ISimCustomSimCmdFileName_par_tbw" "" "B" "" "" "" "PROP_ISimGenVCDFile_par_tb" "false" @@ -1129,20 +1246,58 @@ proc restore { { project_dir "" } } { "B" "" "" "" "PROP_ISimStoreAllSignalTransitions_par_tb" "false" "B" "" "" "" "PROP_ISimStoreAllSignalTransitions_par_tbw" "false" "B" "" "" "" "PROP_MapEffortLevel" "Medium" + "B" "" "" "" "PROP_MapEquivalentRegisterRemoval" "true" "B" "" "" "" "PROP_MapLogicOptimization" "false" "B" "" "" "" "PROP_MapPlacerCostTable" "1" "B" "" "" "" "PROP_MapPowerReduction" "false" "B" "" "" "" "PROP_MapRegDuplication" "false" + "B" "" "" "" "PROP_MapRetiming" "false" + "B" "" "" "" "PROP_ModelSimConfigName" "Default" + "B" "" "" "" "PROP_ModelSimDataWin" "false" + "B" "" "" "" "PROP_ModelSimListWin" "false" + "B" "" "" "" "PROP_ModelSimProcWin" "false" + "B" "" "" "" "PROP_ModelSimSignalWin" "true" + "B" "" "" "" "PROP_ModelSimSimRes" "Default (1 ps)" + "B" "" "" "" "PROP_ModelSimSimRunTime_tb" "1000ns" + "B" "" "" "" "PROP_ModelSimSimRunTime_tbw" "1000ns" + "B" "" "" "" "PROP_ModelSimSourceWin" "false" + "B" "" "" "" "PROP_ModelSimStructWin" "true" + "B" "" "" "" "PROP_ModelSimUutInstName_postMap" "UUT" + "B" "" "" "" "PROP_ModelSimUutInstName_postPar" "UUT" + "B" "" "" "" "PROP_ModelSimVarsWin" "false" + "B" "" "" "" "PROP_ModelSimWaveWin" "true" + "B" "" "" "" "PROP_PrecNumOfCriticalPaths" "1" + "B" "" "" "" "PROP_PrecNumOfSumPaths" "10" + "B" "" "" "" "PROP_SimCustom_behav" "" + "B" "" "" "" "PROP_SimCustom_launchMSim" "" + "B" "" "" "" "PROP_SimCustom_postMap" "" + "B" "" "" "" "PROP_SimCustom_postPar" "" + "B" "" "" "" "PROP_SimCustom_postXlate" "" + "B" "" "" "" "PROP_SimGenVcdFile" "false" "B" "" "" "" "PROP_SimModelRenTopLevInstTo" "UUT" + "B" "" "" "" "PROP_SimSyntax" "93" + "B" "" "" "" "PROP_SimUseExpDeclOnly" "true" + "B" "" "" "" "PROP_SimUserCompileList_behav" "" "B" "" "" "" "PROP_Simulator" "ISE Simulator (VHDL/Verilog)" - "B" "" "" "" "PROP_SmartGuideFileName" "_guide.ncd" + "B" "" "" "" "PROP_SmartGuideFileName" "main_guide.ncd" "B" "" "" "" "PROP_SynthConstraintsFile" "" "B" "" "" "" "PROP_SynthMuxStyle" "Auto" "B" "" "" "" "PROP_SynthRAMStyle" "Auto" "B" "" "" "" "PROP_XPowerOptAdvancedVerboseRpt" "false" "B" "" "" "" "PROP_XPowerOptMaxNumberLines" "1000" + "B" "" "" "" "PROP_XplorerEnableRetiming" "true" + "B" "" "" "" "PROP_XplorerNumIterations" "7" + "B" "" "" "" "PROP_XplorerOtherCmdLineOptions" "" + "B" "" "" "" "PROP_XplorerRunType" "Yes" + "B" "" "" "" "PROP_XplorerWarnToBackup" "true" + "B" "" "" "" "PROP_bitgen_Encrypt_Encrypt" "false" + "B" "" "" "" "PROP_impactBaud" "None" + "B" "" "" "" "PROP_impactConfigFileName" "" + "B" "" "" "" "PROP_impactConfigMode" "None" "B" "" "" "" "PROP_impactPort" "Auto - default" "B" "" "" "" "PROP_mapTimingMode" "Non Timing Driven" + "B" "" "" "" "PROP_mpprViewPadRptForSelRslt" "" + "B" "" "" "" "PROP_mpprViewParRptForSelRslt" "" "B" "" "" "" "PROP_parGenAsyDlyRpt" "false" "B" "" "" "" "PROP_parGenClkRegionRpt" "false" "B" "" "" "" "PROP_parGenSimModel" "false" @@ -1153,6 +1308,9 @@ proc restore { { project_dir "" } } { "B" "" "" "" "PROP_parMpprResultsToSave" "" "B" "" "" "" "PROP_parPowerReduction" "false" "B" "" "" "" "PROP_parTimingMode" "Performance Evaluation" + "B" "" "" "" "PROP_vcom_otherCmdLineOptions" "" + "B" "" "" "" "PROP_vlog_otherCmdLineOptions" "" + "B" "" "" "" "PROP_vsim_otherCmdLineOptions" "" "B" "" "" "" "PROP_xcpldFitDesInReg_xbr" "true" "B" "" "" "" "PROP_xcpldFitDesPtermLmt_xbr" "28" "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_DbgBitStr" "false" @@ -1165,10 +1323,12 @@ proc restore { { project_dir "" } } { "B" "" "" "" "PROP_xstMoveLastFfStage" "true" "B" "" "" "" "PROP_xstROMStyle" "Auto" "B" "" "" "" "PROP_xstSafeImplement" "No" - "B" "AutoGeneratedView" "VIEW_Map" "" "PROP_ParSmartGuideFileName" "_guide.ncd" - "B" "AutoGeneratedView" "VIEW_Translation" "" "PROP_MapSmartGuideFileName" "_guide.ncd" + "B" "AutoGeneratedView" "VIEW_Map" "" "PROP_ParSmartGuideFileName" "main_guide.ncd" + "B" "AutoGeneratedView" "VIEW_Translation" "" "PROP_MapSmartGuideFileName" "main_guide.ncd" "C" "" "" "" "PROP_CompxlibLang" "VHDL" "C" "" "" "" "PROP_CompxlibSimPath" "Search in Path" + "C" "" "" "" "PROP_CompxlibSmartModels" "false" + "C" "" "" "" "PROP_CompxlibUpdateIniForSmartModel" "false" "C" "" "" "" "PROP_DevDevice" "xc3s500e" "C" "" "" "" "PROP_DevFamilyPMName" "spartan3e" "C" "" "" "" "PROP_ISimSimulationRunTime_behav_tb" "1000 ns" @@ -1180,19 +1340,39 @@ proc restore { { project_dir "" } } { "C" "" "" "" "PROP_MapExtraEffort" "None" "C" "" "" "" "PROP_MapPowerActivityFile" "" "C" "" "" "" "PROP_SimModelGenMultiHierFile" "false" + "C" "" "" "" "PROP_bitgen_Encrypt_key0" "" + "C" "" "" "" "PROP_bitgen_Encrypt_key1" "" + "C" "" "" "" "PROP_bitgen_Encrypt_key2" "" + "C" "" "" "" "PROP_bitgen_Encrypt_key3" "" + "C" "" "" "" "PROP_bitgen_Encrypt_key4" "" + "C" "" "" "" "PROP_bitgen_Encrypt_key5" "" + "C" "" "" "" "PROP_bitgen_Encrypt_keyFile" "" "C" "" "" "" "PROP_parPowerActivityFile" "" + "C" "" "" "" "PROP_xilxBitgCfg_GenOpt_ReadBack_virtex2" "false" "C" "" "" "" "PROP_xilxPARextraEffortLevel" "None" "D" "" "" "" "PROP_CompxlibUni9000Lib" "true" "D" "" "" "" "PROP_CompxlibUniSimLib" "true" "D" "" "" "" "PROP_DevPackage" "fg320" "D" "" "" "" "PROP_Synthesis_Tool" "XST (VHDL/Verilog)" + "D" "" "" "" "PROP_xilxBitgCfg_GenOpt_LogicAllocFile_virtex2" "false" + "D" "" "" "" "PROP_xilxBitgCfg_GenOpt_MaskFile_virtex2" "false" + "D" "" "" "" "PROP_xilxBitgReadBk_GenBitStr_virtex2" "false" "E" "" "" "" "PROP_DevSpeed" "-5" "E" "" "" "" "PROP_PreferredLanguage" "VHDL" "F" "" "" "" "PROP_ChangeDevSpeed" "-5" + "F" "" "" "" "PROP_HdlTemplateLang" "VHDL" "F" "" "" "" "PROP_SimModelTarget" "VHDL" + "F" "" "" "" "PROP_coregenFuncModelTargetLang" "VHDL" + "F" "" "" "" "PROP_hdlInstTempTargetLang" "VHDL" + "F" "" "" "" "PROP_schFuncModelTargetLang" "VHDL" + "F" "" "" "" "PROP_schInstTempTargetLang" "VHDL" + "F" "" "" "" "PROP_sysgenInstTempTargetLang" "VHDL" "F" "" "" "" "PROP_tbwTestbenchTargetLang" "VHDL" + "F" "" "" "" "PROP_xawHdlSourceTargetLang" "VHDL" "F" "" "" "" "PROP_xilxPostTrceSpeed" "-5" "F" "" "" "" "PROP_xilxPreTrceSpeed" "-5" + "F" "" "" "" "PROP_xmpInstTempTargetLang" "VHDL" + "G" "" "" "" "PROP_HdlTemplateName" "joshs_svga_controller.vhd" "G" "" "" "" "PROP_SimModelAutoInsertGlblModuleInNetlist" "true" "G" "" "" "" "PROP_SimModelGenArchOnly" "false" "G" "" "" "" "PROP_SimModelIncSdfAnnInVerilogFile" "true" @@ -1203,24 +1383,24 @@ proc restore { { project_dir "" } } { "G" "" "" "" "PROP_SimModelOutputExtIdent" "false" "G" "" "" "" "PROP_SimModelRenTopLevArchTo" "Structure" "G" "" "" "" "PROP_SimModelRenTopLevMod" "" - "G" "" "" "" "PROP_bencherPostMapTestbenchName" "" - "G" "" "" "" "PROP_bencherPostParTestbenchName" "" - "G" "" "" "" "PROP_bencherPostXlateTestbenchName" "" - "G" "" "" "" "PROP_netgenPostMapSimModelName" "_map.vhd" - "G" "" "" "" "PROP_netgenPostParSimModelName" "_timesim.vhd" - "G" "" "" "" "PROP_netgenPostSynthesisSimModelName" "_synthesis.vhd" - "G" "" "" "" "PROP_netgenPostXlateSimModelName" "_translate.vhd" - "G" "AutoGeneratedView" "VIEW_Map" "" "PROP_PostMapSimModelName" "_map.vhd" - "G" "AutoGeneratedView" "VIEW_Par" "" "PROP_PostParSimModelName" "_timesim.vhd" - "G" "AutoGeneratedView" "VIEW_Post-MapAbstractSimulation" "" "PROP_tbwPostMapTestbenchName" "" - "G" "AutoGeneratedView" "VIEW_Post-ParAbstractSimulation" "" "PROP_tbwPostParTestbenchName" "" - "G" "AutoGeneratedView" "VIEW_Post-TranslateAbstractSimulation" "" "PROP_tbwPostXlateTestbenchName" "" - "G" "AutoGeneratedView" "VIEW_Structural" "" "PROP_PostSynthesisSimModelName" "_synthesis.vhd" - "G" "AutoGeneratedView" "VIEW_Translation" "" "PROP_PostXlateSimModelName" "_translate.vhd" + "G" "" "" "" "PROP_bencherPostMapTestbenchName" "main.map_vhw" + "G" "" "" "" "PROP_bencherPostParTestbenchName" "main.timesim_vhw" + "G" "" "" "" "PROP_bencherPostXlateTestbenchName" "main.translate_vhw" + "G" "" "" "" "PROP_netgenPostMapSimModelName" "main_map.vhd" + "G" "" "" "" "PROP_netgenPostParSimModelName" "main_timesim.vhd" + "G" "" "" "" "PROP_netgenPostSynthesisSimModelName" "main_synthesis.vhd" + "G" "" "" "" "PROP_netgenPostXlateSimModelName" "main_translate.vhd" + "G" "AutoGeneratedView" "VIEW_Map" "" "PROP_PostMapSimModelName" "main_map.vhd" + "G" "AutoGeneratedView" "VIEW_Par" "" "PROP_PostParSimModelName" "main_timesim.vhd" + "G" "AutoGeneratedView" "VIEW_Post-MapAbstractSimulation" "" "PROP_tbwPostMapTestbenchName" "main.map_vhw" + "G" "AutoGeneratedView" "VIEW_Post-ParAbstractSimulation" "" "PROP_tbwPostParTestbenchName" "main.timesim_vhw" + "G" "AutoGeneratedView" "VIEW_Post-TranslateAbstractSimulation" "" "PROP_tbwPostXlateTestbenchName" "main.translate_vhw" + "G" "AutoGeneratedView" "VIEW_Structural" "" "PROP_PostSynthesisSimModelName" "main_synthesis.vhd" + "G" "AutoGeneratedView" "VIEW_Translation" "" "PROP_PostXlateSimModelName" "main_translate.vhd" "H" "" "" "" "PROP_SimModelBringOutGsrNetAsAPort" "false" "H" "" "" "" "PROP_SimModelBringOutGtsNetAsAPort" "false" "H" "" "" "" "PROP_SimModelPathUsedInSdfAnn" "Default" - "H" "" "" "" "PROP_netgenRenameTopLevEntTo" "" + "H" "" "" "" "PROP_netgenRenameTopLevEntTo" "main" "I" "" "" "" "PROP_SimModelGsrPortName" "GSR_PORT" "I" "" "" "" "PROP_SimModelGtsPortName" "GTS_PORT" "I" "" "" "" "PROP_SimModelRocPulseWidth" "100" diff --git a/joshs_svga_controller/joshs_svga_controller.vhd b/joshs_svga_controller/joshs_svga_controller.vhd new file mode 100644 index 0000000..4970800 --- /dev/null +++ b/joshs_svga_controller/joshs_svga_controller.vhd @@ -0,0 +1,96 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 19:51:36 06/05/2008 +-- Design Name: +-- Module Name: joshs_svga_controller - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity joshs_svga_controller is + Port + ( + clk_50mhz : in STD_LOGIC; + vgaHSync : out STD_LOGIC; + vgaVSync : out STD_LOGIC; + vgaBlank : out STD_LOGIC; + hCount : out STD_LOGIC_VECTOR (10 downto 0); + vCount : out STD_LOGIC_VECTOR (9 downto 0) + ); +end joshs_svga_controller; + +architecture Behavioral of joshs_svga_controller is + + constant H_RES : integer := 800; + constant V_RES : integer := 600; + constant H_MIN : integer := -184; + constant H_MAX : integer := 855; + constant V_MIN : integer := -29; + constant V_MAX : integer := 636; + constant H_SYNC_END : integer := H_MIN+120-1; + constant V_SYNC_END : integer := V_MIN+6-1; + +begin + + svgaProcess : process (clk_50mhz) is + variable hCounter : integer range H_MIN to H_MAX := H_MAX; + variable vCounter : integer range H_MIN to V_MAX := V_MAX; + begin + if (rising_edge(clk_50mhz)) then + -- update the counters + if (hCounter = H_MAX) then + hCounter := 0; + vgaHSync <= '0'; + if (vCounter = V_MAX) then + vCounter := 0; + vgaVSync <= '0'; + else + if (vCounter = V_SYNC_END) then + vgaVSync <= '1'; + end if; + vCounter := vCounter + 1; + end if; + else + if (hCounter = H_SYNC_END) then + vgaHSync <= '1'; + end if; + hCounter := hCounter + 1; + end if; + + -- update blank + if (vCounter >= 0 and + vCounter < V_RES and + hCounter >= 0 and + hCounter < H_RES) then + vgaBlank <= '1'; + else + vgaBlank <= '0'; + end if; + + hCount <= conv_std_logic_vector(hCounter, 11); + vCount <= conv_std_logic_vector(vCounter, 10); + end if; + end process; + +end Behavioral; + diff --git a/joshs_svga_controller/main.vhd b/joshs_svga_controller/main.vhd new file mode 100644 index 0000000..cc20da4 --- /dev/null +++ b/joshs_svga_controller/main.vhd @@ -0,0 +1,97 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 19:49:49 06/05/2008 +-- Design Name: +-- Module Name: main - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity main is + Port + ( + clk50mhz : in STD_LOGIC; + switches : in STD_LOGIC_VECTOR (7 downto 0); +-- buttons : in STD_LOGIC_VECTOR (3 downto 0); + vgaR : out STD_LOGIC_VECTOR (2 downto 0); + vgaG : out STD_LOGIC_VECTOR (2 downto 0); + vgaB : out STD_LOGIC_VECTOR (1 downto 0); + vgaHSync : out STD_LOGIC; + vgaVSync : out STD_LOGIC + ); +end main; + +architecture Behavioral of main is + + component joshs_svga_controller is + Port + ( + clk_50mhz : in STD_LOGIC; + vgaHSync : out STD_LOGIC; + vgaVSync : out STD_LOGIC; + vgaBlank : out STD_LOGIC; + hCount : out STD_LOGIC_VECTOR (10 downto 0); + vCount : out STD_LOGIC_VECTOR (9 downto 0) + ); + end component; + + signal vgaBlank : STD_LOGIC; + signal hCount : STD_LOGIC_VECTOR(10 downto 0); + signal vCount : STD_LOGIC_VECTOR(9 downto 0); + +begin + + vgaController : joshs_svga_controller + port map + ( + clk_50mhz => clk50mhz, + vgaHSync => vgaHSync, + vgaVSync => vgaVSync, + vgaBlank => vgaBlank, + hCount => hCount, + vCount => vCount + ); + + pixelDrawar : process(hCount, vCount, vgaBlank) is + begin + if (vgaBlank = '1') then + vgaR <= "000"; + vgaG <= "000"; + vgaB <= "00"; + elsif (hCount < 100) then + vgaR <= switches(7 downto 5); + vgaG <= switches(4 downto 2); + vgaB <= switches(1 downto 0); + elsif (vCount > 200) then + vgaR <= "111"; + vgaG <= "111"; + vgaB <= "11"; + else + vgaR <= "111"; + vgaG <= "111"; + vgaB <= "00"; + end if; + end process; + +end Behavioral; + diff --git a/joshs_svga_controller/nexys2.ucf b/joshs_svga_controller/nexys2.ucf new file mode 100644 index 0000000..f22f231 --- /dev/null +++ b/joshs_svga_controller/nexys2.ucf @@ -0,0 +1,101 @@ +NET "clk50mhz" LOC = "B8"; + +NET "switches<0>" LOC = "G18"; +NET "switches<1>" LOC = "H18"; +NET "switches<2>" LOC = "K18"; +NET "switches<3>" LOC = "K17"; +NET "switches<4>" LOC = "L14"; +NET "switches<5>" LOC = "L13"; +NET "switches<6>" LOC = "N17"; +NET "switches<7>" LOC = "R17"; + +#NET "leds<0>" LOC = "J14"; +#NET "leds<1>" LOC = "J15"; +#NET "leds<2>" LOC = "K15"; +#NET "leds<3>" LOC = "K14"; +#NET "leds<4>" LOC = "E17"; +#NET "leds<5>" LOC = "P15"; +#NET "leds<6>" LOC = "F4"; +#NET "leds<7>" LOC = "R4"; + +#NET "buttons<0>" LOC = "H13"; +#NET "buttons<1>" LOC = "E18"; +#NET "buttons<2>" LOC = "D18"; +#NET "buttons<3>" LOC = "B18"; + +#NET "sevenseg<0>" LOC = "C17"; +#NET "sevenseg<1>" LOC = "H14"; +#NET "sevenseg<2>" LOC = "J17"; +#NET "sevenseg<3>" LOC = "G14"; +#NET "sevenseg<4>" LOC = "D16"; +#NET "sevenseg<5>" LOC = "D17"; +#NET "sevenseg<6>" LOC = "F18"; +#NET "sevenseg<7>" LOC = "L18"; + +#NET "sevenseganodes<0>" LOC = "F17"; +#NET "sevenseganodes<1>" LOC = "H17"; +#NET "sevenseganodes<2>" LOC = "C18"; +#NET "sevenseganodes<3>" LOC = "F15"; + +NET "vgaHsync" LOC = "T4"; +NET "vgaVsync" LOC = "U3"; +NET "vgaR<0>" LOC = "R9"; +NET "vgaR<1>" LOC = "T8"; +NET "vgaR<2>" LOC = "R8"; +NET "vgaG<0>" LOC = "N8"; +NET "vgaG<1>" LOC = "P8"; +NET "vgaG<2>" LOC = "P6"; +NET "vgaB<0>" LOC = "U5"; +NET "vgaB<1>" LOC = "U4"; + +#NET "ramAddr<0>" LOC= "J1"; # Bank = 3 , Pin name = IO_L12P_3/LHCLK2 , Type = LHCLK , Sch name = ADR1 +#NET "ramAddr<1>" LOC= "J2"; # Bank = 3 , Pin name = IO_L12N_3/LHCLK3/IRDY2 , Type = LHCLK , Sch name = ADR2 +#NET "ramAddr<2>" LOC= "H4"; # Bank = 3 , Pin name = IO_L09P_3 , Type = I/O , Sch name = ADR3 +#NET "ramAddr<3>" LOC= "H1"; # Bank = 3 , Pin name = IO_L10N_3 , Type = I/O , Sch name = ADR4 +#NET "ramAddr<4>" LOC= "H2"; # Bank = 3 , Pin name = IO_L10P_3 , Type = I/O , Sch name = ADR5 +#NET "ramAddr<5>" LOC= "J5"; # Bank = 3 , Pin name = IO_L11P_3/LHCLK0 , Type = LHCLK , Sch name = ADR6 +#NET "ramAddr<6>" LOC= "H3"; # Bank = 3 , Pin name = IO_L09N_3 , Type = I/O , Sch name = ADR7 +#NET "ramAddr<7>" LOC= "H6"; # Bank = 3 , Pin name = IO_L08P_3 , Type = I/O , Sch name = ADR8 +#NET "ramAddr<8>" LOC= "F1"; # Bank = 3 , Pin name = IO_L05P_3 , Type = I/O , Sch name = ADR9 +#NET "ramAddr<9>" LOC= "G3"; # Bank = 3 , Pin name = IO_L06P_3 , Type = I/O , Sch name = ADR10 +#NET "ramAddr<10>" LOC= "G6"; # Bank = 3 , Pin name = IO_L07P_3 , Type = I/O , Sch name = ADR11 +#NET "ramAddr<11>" LOC= "G5"; # Bank = 3 , Pin name = IO_L07N_3 , Type = I/O , Sch name = ADR12 +#NET "ramAddr<12>" LOC= "G4"; # Bank = 3 , Pin name = IO_L06N_3/VREF_3 , Type = VREF , Sch name = ADR13 +#NET "ramAddr<13>" LOC= "F2"; # Bank = 3 , Pin name = IO_L05N_3 , Type = I/O , Sch name = ADR14 +#NET "ramAddr<14>" LOC= "E1"; # Bank = 3 , Pin name = IO_L03N_3 , Type = I/O , Sch name = ADR15 +#NET "ramAddr<15>" LOC= "M5"; # Bank = 3 , Pin name = IO_L19P_3 , Type = I/O , Sch name = ADR16 +#NET "ramAddr<16>" LOC= "E2"; # Bank = 3 , Pin name = IO_L03P_3 , Type = I/O , Sch name = ADR17 +#NET "ramAddr<17>" LOC= "C2"; # Bank = 3 , Pin name = IO_L01N_3 , Type = I/O , Sch name = ADR18 +#NET "ramAddr<18>" LOC= "C1"; # Bank = 3 , Pin name = IO_L01P_3 , Type = I/O , Sch name = ADR19 +#NET "ramAddr<19>" LOC= "D2"; # Bank = 3 , Pin name = IO_L02N_3/VREF_3 , Type = VREF , Sch name = ADR20 +#NET "ramAddr<20>" LOC= "K3"; # Bank = 3 , Pin name = IO_L13P_3/LHCLK4/TRDY2 , Type = LHCLK , Sch name = ADR21 +#NET "ramAddr<21>" LOC= "D1"; # Bank = 3 , Pin name = IO_L02P_3 , Type = I/O , Sch name = ADR22 +#NET "ramAddr<22>" LOC= "K6"; # Bank = 3 , Pin name = IO_L14P_3/LHCLK6 , Type = LHCLK , Sch name = ADR23 + +#NET "ramData<0>" LOC= "L1"; # Bank = 3 , Pin name = IO_L15P_3 , Type = I/O , Sch name = DB0 +#NET "ramData<1>" LOC= "L4"; # Bank = 3 , Pin name = IO_L16N_3 , Type = I/O , Sch name = DB1 +#NET "ramData<2>" LOC= "L6"; # Bank = 3 , Pin name = IO_L17P_3 , Type = I/O , Sch name = DB2 +#NET "ramData<3>" LOC= "M4"; # Bank = 3 , Pin name = IO_L18P_3 , Type = I/O , Sch name = DB3 +#NET "ramData<4>" LOC= "N5"; # Bank = 3 , Pin name = IO_L20N_3 , Type = I/O , Sch name = DB4 +#NET "ramData<5>" LOC= "P1"; # Bank = 3 , Pin name = IO_L21N_3 , Type = I/O , Sch name = DB5 +#NET "ramData<6>" LOC= "P2"; # Bank = 3 , Pin name = IO_L21P_3 , Type = I/O , Sch name = DB6 +#NET "ramData<7>" LOC= "R2"; # Bank = 3 , Pin name = IO_L23N_3 , Type = I/O , Sch name = DB7 +#NET "ramData<8>" LOC= "L3"; # Bank = 3 , Pin name = IO_L16P_3 , Type = I/O , Sch name = DB8 +#NET "ramData<9>" LOC= "L5"; # Bank = 3 , Pin name = IO_L17N_3/VREF_3 , Type = VREF , Sch name = DB9 +#NET "ramData<10>" LOC= "M3"; # Bank = 3 , Pin name = IO_L18N_3 , Type = I/O , Sch name = DB10 +#NET "ramData<11>" LOC= "M6"; # Bank = 3 , Pin name = IO_L19N_3 , Type = I/O , Sch name = DB11 +#NET "ramData<12>" LOC= "L2"; # Bank = 3 , Pin name = IO_L15N_3 , Type = I/O , Sch name = DB12 +#NET "ramData<13>" LOC= "N4"; # Bank = 3 , Pin name = IO_L20P_3 , Type = I/O , Sch name = DB13 +#NET "ramData<14>" LOC= "R3"; # Bank = 3 , Pin name = IO_L23P_3 , Type = I/O , Sch name = DB14 +#NET "ramData<15>" LOC= "T1"; # Bank = 3 , Pin name = IO_L24N_3 , Type = I/O , Sch name = DB15 + +#NET "ramClk" LOC = "H5"; +#NET "ramCE_n" LOC = "R6"; +#NET "ramADV_n" LOC = "J4"; +#NET "ramUB_n" LOC = "K4"; +#NET "ramLB_n" LOC = "K5"; +#NET "ramCRE" LOC = "P7"; +#NET "ramOE_n" LOC = "T2"; +#NET "ramWE_n" LOC = "N7"; +#NET "ramWait" LOC = "F5"; +