----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:51:36 06/05/2008 
-- Design Name: 
-- Module Name:    joshs_svga_controller - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity joshs_svga_controller is
    Port
    (
        clk_50mhz : in  STD_LOGIC;
        vgaHSync  : out STD_LOGIC;
        vgaVSync  : out STD_LOGIC;
        vgaBlank  : out STD_LOGIC;
        hCount    : out STD_LOGIC_VECTOR (10 downto 0);
        vCount    : out STD_LOGIC_VECTOR (9 downto 0)
    );
end joshs_svga_controller;

architecture Behavioral of joshs_svga_controller is

    constant H_RES : std_logic_vector(10 downto 0) := conv_std_logic_vector(800, 11);
    constant V_RES : std_logic_vector(9 downto 0) := conv_std_logic_vector(600, 10);
    constant H_MAX : std_logic_vector(10 downto 0) := conv_std_logic_vector(1039, 11);
    constant V_MAX : std_logic_vector(9 downto 0) := conv_std_logic_vector(665, 10);
    constant H_SYNC_BEGIN : std_logic_vector(10 downto 0) := conv_std_logic_vector(864, 11);
    constant H_SYNC_END : std_logic_vector(10 downto 0) := conv_std_logic_vector(983, 11);
    constant V_SYNC_BEGIN : std_logic_vector(9 downto 0) := conv_std_logic_vector(623, 10);
    constant V_SYNC_END : std_logic_vector(9 downto 0) := conv_std_logic_vector(628, 10);
    constant H_SYNC_PULSE : std_logic := '1';
    constant V_SYNC_PULSE : std_logic := '1';

    signal hCounter : std_logic_vector(10 downto 0) := conv_std_logic_vector(0, 11);
    signal vCounter : std_logic_vector(9 downto 0) := conv_std_logic_vector(0, 10);

    signal video_enable : std_logic;
begin

    hCount <= hCounter;
    vCount <= vCounter;

    vgaBlank <= not video_enable when rising_edge(clk_50mhz);

    h_count : process (clk_50mhz) is
    begin
        if (rising_edge(clk_50mhz)) then
            if (hCounter = H_MAX) then
                hCounter <= conv_std_logic_vector(0, 11);
            else
                hCounter <= hCounter + 1;
            end if;
        end if;
    end process;

    v_count : process (clk_50mhz) is
    begin
        if (rising_edge(clk_50mhz)) then
            if (hCounter = H_MAX) then
                if (vCounter = V_MAX) then
                    vCounter <= conv_std_logic_vector(0, 10);
                else
                    vCounter <= vCounter + 1;
                end if;
            end if;
        end if;
    end process;

    h_sync : process (clk_50mhz) is
    begin
        if (rising_edge(clk_50mhz)) then
            if (hCounter >= H_SYNC_BEGIN and hCounter <= H_SYNC_END)then
                vgaHSync <= H_SYNC_PULSE;
            else
                vgaHSync <= not H_SYNC_PULSE;
            end if;
        end if;
    end process;

    v_sync : process (clk_50mhz) is
    begin
        if (rising_edge(clk_50mhz)) then
            if (vCounter >= V_SYNC_BEGIN and vCounter <= V_SYNC_END)then
                vgaVSync <= V_SYNC_PULSE;
            else
                vgaVSync <= not V_SYNC_PULSE;
            end if;
        end if;
    end process;

    blankProcess : process (clk_50mhz) is
    begin
        if (rising_edge(clk_50mhz)) then
        end if;
    end process;

    video_enable <= '1' when (hCounter < H_RES and vCounter < V_RES) else '0';

end Behavioral;