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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:49:49 06/05/2008 
-- Design Name: 
-- Module Name:    main - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
    Port
    (
        clk50mhz : in  STD_LOGIC;
        switches : in  STD_LOGIC_VECTOR (7 downto 0);
--        buttons  : in  STD_LOGIC_VECTOR (3 downto 0);
        vgaR     : out STD_LOGIC_VECTOR (2 downto 0);
        vgaG     : out STD_LOGIC_VECTOR (2 downto 0);
        vgaB     : out STD_LOGIC_VECTOR (1 downto 0);
        vgaHSync : out STD_LOGIC;
        vgaVSync : out STD_LOGIC
    );
end main;

architecture Behavioral of main is

    component joshs_svga_controller is
        Port
        (
            clk_50mhz : in  STD_LOGIC;
            vgaHSync  : out STD_LOGIC;
            vgaVSync  : out STD_LOGIC;
            vgaBlank  : out STD_LOGIC;
            hCount    : out STD_LOGIC_VECTOR (10 downto 0);
            vCount    : out STD_LOGIC_VECTOR (9 downto 0)
        );
    end component;

    signal vgaBlank : STD_LOGIC;
    signal hCount   : STD_LOGIC_VECTOR(10 downto 0);
    signal vCount   : STD_LOGIC_VECTOR(9 downto 0);

begin

    vgaController : joshs_svga_controller
        port map
        (
            clk_50mhz => clk50mhz,
            vgaHSync  => vgaHSync,
            vgaVSync  => vgaVSync,
            vgaBlank  => vgaBlank,
            hCount    => hCount,
            vCount    => vCount
        );

    pixelDrawar : process(hCount, vCount, vgaBlank) is
    begin
        if (vgaBlank = '1') then
            vgaR <= "000";
            vgaG <= "000";
            vgaB <= "00";
        elsif (hCount < 100) then
            vgaR <= switches(7 downto 5);
            vgaG <= switches(4 downto 2);
            vgaB <= switches(1 downto 0);
        elsif (vCount > 200) then
            vgaR <= "111";
            vgaG <= "111";
            vgaB <= "11";
        else
            vgaR <= "111";
            vgaG <= "111";
            vgaB <= "00";
        end if;
    end process;

end Behavioral;