----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:51:36 06/05/2008 
-- Design Name: 
-- Module Name:    joshs_svga_controller - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity joshs_svga_controller is
    Port
    (
        clk_50mhz : in  STD_LOGIC;
        vgaHSync  : out STD_LOGIC;
        vgaVSync  : out STD_LOGIC;
        vgaBlank  : out STD_LOGIC;
        hCount    : out STD_LOGIC_VECTOR (10 downto 0);
        vCount    : out STD_LOGIC_VECTOR (9 downto 0)
    );
end joshs_svga_controller;

architecture Behavioral of joshs_svga_controller is

    constant H_RES : integer := 800;
    constant V_RES : integer := 600;
    constant H_MIN : integer := -184;
    constant H_MAX : integer := 855;
    constant V_MIN : integer := -29;
    constant V_MAX : integer := 636;
    constant H_SYNC_END : integer := H_MIN+120-1;
    constant V_SYNC_END : integer := V_MIN+6-1;

begin

    svgaProcess : process (clk_50mhz) is
        variable hCounter : integer range H_MIN to H_MAX := H_MAX;
        variable vCounter : integer range H_MIN to V_MAX := V_MAX;
    begin
        if (rising_edge(clk_50mhz)) then
            -- update the counters
            if (hCounter = H_MAX) then
                hCounter := 0;
                vgaHSync <= '0';
                if (vCounter = V_MAX) then
                    vCounter := 0;
                    vgaVSync <= '0';
                else
                    if (vCounter = V_SYNC_END) then
                        vgaVSync <= '1';
                    end if;
                    vCounter := vCounter + 1;
                end if;
            else
                if (hCounter = H_SYNC_END) then
                    vgaHSync <= '1';
                end if;
                hCounter := hCounter + 1;
            end if;

            -- update blank
            if (vCounter >= 0 and
                vCounter <  V_RES and
                hCounter >= 0 and
                hCounter <  H_RES) then
                vgaBlank <= '1';
            else
                vgaBlank <= '0';
            end if;

            hCount <= conv_std_logic_vector(hCounter, 11);
            vCount <= conv_std_logic_vector(vCounter, 10);
        end if;
    end process;

end Behavioral;