122 lines
3.8 KiB
VHDL
122 lines
3.8 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 19:51:36 06/05/2008
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-- Design Name:
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-- Module Name: joshs_svga_controller - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity joshs_svga_controller is
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Port
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(
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clk_50mhz : in STD_LOGIC;
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vgaHSync : out STD_LOGIC;
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vgaVSync : out STD_LOGIC;
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vgaBlank : out STD_LOGIC;
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hCount : out STD_LOGIC_VECTOR (10 downto 0);
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vCount : out STD_LOGIC_VECTOR (9 downto 0)
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);
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end joshs_svga_controller;
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architecture Behavioral of joshs_svga_controller is
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constant H_RES : std_logic_vector(10 downto 0) := conv_std_logic_vector(800, 11);
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constant V_RES : std_logic_vector(9 downto 0) := conv_std_logic_vector(600, 10);
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constant H_MAX : std_logic_vector(10 downto 0) := conv_std_logic_vector(1039, 11);
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constant V_MAX : std_logic_vector(9 downto 0) := conv_std_logic_vector(665, 10);
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constant H_SYNC_BEGIN : std_logic_vector(10 downto 0) := conv_std_logic_vector(864, 11);
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constant H_SYNC_END : std_logic_vector(10 downto 0) := conv_std_logic_vector(983, 11);
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constant V_SYNC_BEGIN : std_logic_vector(9 downto 0) := conv_std_logic_vector(623, 10);
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constant V_SYNC_END : std_logic_vector(9 downto 0) := conv_std_logic_vector(628, 10);
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constant H_SYNC_PULSE : std_logic := '1';
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constant V_SYNC_PULSE : std_logic := '1';
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signal hCounter : std_logic_vector(10 downto 0) := conv_std_logic_vector(0, 11);
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signal vCounter : std_logic_vector(9 downto 0) := conv_std_logic_vector(0, 10);
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signal video_enable : std_logic;
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begin
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hCount <= hCounter;
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vCount <= vCounter;
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vgaBlank <= not video_enable when rising_edge(clk_50mhz);
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h_count : process (clk_50mhz) is
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begin
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if (rising_edge(clk_50mhz)) then
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if (hCounter = H_MAX) then
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hCounter <= conv_std_logic_vector(0, 11);
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else
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hCounter <= hCounter + 1;
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end if;
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end if;
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end process;
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v_count : process (clk_50mhz) is
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begin
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if (rising_edge(clk_50mhz)) then
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if (hCounter = H_MAX) then
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if (vCounter = V_MAX) then
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vCounter <= conv_std_logic_vector(0, 10);
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else
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vCounter <= vCounter + 1;
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end if;
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end if;
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end if;
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end process;
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h_sync : process (clk_50mhz) is
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begin
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if (rising_edge(clk_50mhz)) then
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if (hCounter >= H_SYNC_BEGIN and hCounter <= H_SYNC_END)then
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vgaHSync <= H_SYNC_PULSE;
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else
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vgaHSync <= not H_SYNC_PULSE;
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end if;
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end if;
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end process;
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v_sync : process (clk_50mhz) is
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begin
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if (rising_edge(clk_50mhz)) then
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if (vCounter >= V_SYNC_BEGIN and vCounter <= V_SYNC_END)then
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vgaVSync <= V_SYNC_PULSE;
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else
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vgaVSync <= not V_SYNC_PULSE;
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end if;
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end if;
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end process;
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blankProcess : process (clk_50mhz) is
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begin
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if (rising_edge(clk_50mhz)) then
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end if;
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end process;
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video_enable <= '1' when (hCounter < H_RES and vCounter < V_RES) else '0';
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end Behavioral;
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