90 lines
2.0 KiB
D
90 lines
2.0 KiB
D
/**
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* eXtensible Host Controller Interface for Universal Serial Bus
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*
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* Documentation:
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* - https://wiki.osdev.org/EXtensible_Host_Controller_Interface
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* - https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf
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*/
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module hulk.usb.xhci;
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import hulk.pci;
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import hulk.hurl.a1;
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struct XHCI
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{
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/**
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* Located at PCI base address.
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*/
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struct CapabilityRegisters
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{
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ubyte capability_length;
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ubyte _reserved01;
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ushort hci_version;
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uint[3] hcs_params;
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uint hcc_params1;
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uint doorbell_offset;
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uint rts_offset;
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uint hcc_params2;
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}
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static assert(CapabilityRegisters.sizeof == 0x20u);
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/**
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* Located at offset capability_length from PCI base address.
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*/
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struct OperationalRegisters
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{
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uint usb_command;
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uint usb_status;
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uint page_size;
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uint[2] _reserved01;
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uint dn_ctrl;
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ulong cr_ctrl;
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uint[4] _reserved02;
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ulong dcbaap;
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uint config;
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uint _reserved03;
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}
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static assert(OperationalRegisters.sizeof == 0x40u);
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/**
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* Located at offset 0x400 from start of Operational Registers.
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*/
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struct PortRegisters
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{
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uint portsc;
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uint portpmsc;
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uint portli;
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uint porthlpmc;
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}
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static assert(PortRegisters.sizeof == 0x10u);
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struct RuntimeRegisters
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{
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uint mfindex;
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uint[7] _reserved01;
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uint ir;
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}
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struct DoorbellRegister
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{
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ubyte target;
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ubyte _reserved01;
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ushort task_id;
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}
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static assert(DoorbellRegister.sizeof == 4u);
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void initialize(Pci.Device * pci_device)
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{
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}
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static void build(Pci.Device * pci_device)
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{
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if (pci_device.memory_ranges[0].address != null)
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{
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XHCI * xhci = A1.allocate!XHCI();
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xhci.initialize(pci_device);
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}
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}
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}
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