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rewritten SVGA controller works for 800x600@72Hz!

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git-svn-id: svn://anubis/nexys2@4 75d2ff46-95cb-4c49-a3ed-7201f6c6b742
This commit is contained in:
josh 2008-06-06 01:26:50 +00:00
parent 988d85da2c
commit bf5147052f
2 changed files with 65 additions and 40 deletions
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joshs_svga_controller/joshs_svga_controller.ise
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joshs_svga_controller/joshs_svga_controller.vhd
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@ -41,56 +41,81 @@ end joshs_svga_controller;
architecture Behavioral of joshs_svga_controller is architecture Behavioral of joshs_svga_controller is
constant H_RES : integer := 800; constant H_RES : std_logic_vector(10 downto 0) := conv_std_logic_vector(800, 11);
constant V_RES : integer := 600; constant V_RES : std_logic_vector(9 downto 0) := conv_std_logic_vector(600, 10);
constant H_MIN : integer := -184; constant H_MAX : std_logic_vector(10 downto 0) := conv_std_logic_vector(1039, 11);
constant H_MAX : integer := 855; constant V_MAX : std_logic_vector(9 downto 0) := conv_std_logic_vector(665, 10);
constant V_MIN : integer := -29; constant H_SYNC_BEGIN : std_logic_vector(10 downto 0) := conv_std_logic_vector(864, 11);
constant V_MAX : integer := 636; constant H_SYNC_END : std_logic_vector(10 downto 0) := conv_std_logic_vector(983, 11);
constant H_SYNC_END : integer := H_MIN+120-1; constant V_SYNC_BEGIN : std_logic_vector(9 downto 0) := conv_std_logic_vector(623, 10);
constant V_SYNC_END : integer := V_MIN+6-1; constant V_SYNC_END : std_logic_vector(9 downto 0) := conv_std_logic_vector(628, 10);
constant H_SYNC_PULSE : std_logic := '1';
constant V_SYNC_PULSE : std_logic := '1';
signal hCounter : std_logic_vector(10 downto 0) := conv_std_logic_vector(0, 11);
signal vCounter : std_logic_vector(9 downto 0) := conv_std_logic_vector(0, 10);
signal video_enable : std_logic;
begin begin
svgaProcess : process (clk_50mhz) is hCount <= hCounter;
variable hCounter : integer range H_MIN to H_MAX := H_MAX; vCount <= vCounter;
variable vCounter : integer range H_MIN to V_MAX := V_MAX;
vgaBlank <= not video_enable when rising_edge(clk_50mhz);
h_count : process (clk_50mhz) is
begin begin
if (rising_edge(clk_50mhz)) then if (rising_edge(clk_50mhz)) then
-- update the counters
if (hCounter = H_MAX) then if (hCounter = H_MAX) then
hCounter := 0; hCounter <= conv_std_logic_vector(0, 11);
vgaHSync <= '0';
if (vCounter = V_MAX) then
vCounter := 0;
vgaVSync <= '0';
else else
if (vCounter = V_SYNC_END) then hCounter <= hCounter + 1;
vgaVSync <= '1';
end if; end if;
vCounter := vCounter + 1;
end if;
else
if (hCounter = H_SYNC_END) then
vgaHSync <= '1';
end if;
hCounter := hCounter + 1;
end if;
-- update blank
if (vCounter >= 0 and
vCounter < V_RES and
hCounter >= 0 and
hCounter < H_RES) then
vgaBlank <= '1';
else
vgaBlank <= '0';
end if;
hCount <= conv_std_logic_vector(hCounter, 11);
vCount <= conv_std_logic_vector(vCounter, 10);
end if; end if;
end process; end process;
v_count : process (clk_50mhz) is
begin
if (rising_edge(clk_50mhz)) then
if (hCounter = H_MAX) then
if (vCounter = V_MAX) then
vCounter <= conv_std_logic_vector(0, 10);
else
vCounter <= vCounter + 1;
end if;
end if;
end if;
end process;
h_sync : process (clk_50mhz) is
begin
if (rising_edge(clk_50mhz)) then
if (hCounter >= H_SYNC_BEGIN and hCounter <= H_SYNC_END)then
vgaHSync <= H_SYNC_PULSE;
else
vgaHSync <= not H_SYNC_PULSE;
end if;
end if;
end process;
v_sync : process (clk_50mhz) is
begin
if (rising_edge(clk_50mhz)) then
if (vCounter >= V_SYNC_BEGIN and vCounter <= V_SYNC_END)then
vgaVSync <= V_SYNC_PULSE;
else
vgaVSync <= not V_SYNC_PULSE;
end if;
end if;
end process;
blankProcess : process (clk_50mhz) is
begin
if (rising_edge(clk_50mhz)) then
end if;
end process;
video_enable <= '1' when (hCounter < H_RES and vCounter < V_RES) else '0';
end Behavioral; end Behavioral;