98 lines
2.6 KiB
VHDL
98 lines
2.6 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 19:49:49 06/05/2008
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-- Design Name:
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-- Module Name: main - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity main is
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Port
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(
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clk50mhz : in STD_LOGIC;
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switches : in STD_LOGIC_VECTOR (7 downto 0);
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-- buttons : in STD_LOGIC_VECTOR (3 downto 0);
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vgaR : out STD_LOGIC_VECTOR (2 downto 0);
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vgaG : out STD_LOGIC_VECTOR (2 downto 0);
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vgaB : out STD_LOGIC_VECTOR (1 downto 0);
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vgaHSync : out STD_LOGIC;
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vgaVSync : out STD_LOGIC
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);
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end main;
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architecture Behavioral of main is
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component joshs_svga_controller is
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Port
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(
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clk_50mhz : in STD_LOGIC;
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vgaHSync : out STD_LOGIC;
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vgaVSync : out STD_LOGIC;
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vgaBlank : out STD_LOGIC;
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hCount : out STD_LOGIC_VECTOR (10 downto 0);
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vCount : out STD_LOGIC_VECTOR (9 downto 0)
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);
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end component;
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signal vgaBlank : STD_LOGIC;
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signal hCount : STD_LOGIC_VECTOR(10 downto 0);
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signal vCount : STD_LOGIC_VECTOR(9 downto 0);
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begin
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vgaController : joshs_svga_controller
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port map
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(
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clk_50mhz => clk50mhz,
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vgaHSync => vgaHSync,
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vgaVSync => vgaVSync,
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vgaBlank => vgaBlank,
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hCount => hCount,
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vCount => vCount
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);
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pixelDrawar : process(hCount, vCount, vgaBlank) is
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begin
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if (vgaBlank = '1') then
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vgaR <= "000";
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vgaG <= "000";
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vgaB <= "00";
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elsif (hCount < 100) then
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vgaR <= switches(7 downto 5);
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vgaG <= switches(4 downto 2);
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vgaB <= switches(1 downto 0);
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elsif (vCount > 200) then
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vgaR <= "111";
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vgaG <= "111";
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vgaB <= "11";
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else
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vgaR <= "111";
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vgaG <= "111";
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vgaB <= "00";
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end if;
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end process;
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end Behavioral;
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