97 lines
2.8 KiB
VHDL
97 lines
2.8 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 19:51:36 06/05/2008
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-- Design Name:
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-- Module Name: joshs_svga_controller - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity joshs_svga_controller is
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Port
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(
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clk_50mhz : in STD_LOGIC;
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vgaHSync : out STD_LOGIC;
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vgaVSync : out STD_LOGIC;
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vgaBlank : out STD_LOGIC;
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hCount : out STD_LOGIC_VECTOR (10 downto 0);
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vCount : out STD_LOGIC_VECTOR (9 downto 0)
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);
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end joshs_svga_controller;
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architecture Behavioral of joshs_svga_controller is
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constant H_RES : integer := 800;
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constant V_RES : integer := 600;
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constant H_MIN : integer := -184;
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constant H_MAX : integer := 855;
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constant V_MIN : integer := -29;
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constant V_MAX : integer := 636;
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constant H_SYNC_END : integer := H_MIN+120-1;
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constant V_SYNC_END : integer := V_MIN+6-1;
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begin
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svgaProcess : process (clk_50mhz) is
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variable hCounter : integer range H_MIN to H_MAX := H_MAX;
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variable vCounter : integer range H_MIN to V_MAX := V_MAX;
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begin
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if (rising_edge(clk_50mhz)) then
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-- update the counters
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if (hCounter = H_MAX) then
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hCounter := 0;
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vgaHSync <= '0';
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if (vCounter = V_MAX) then
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vCounter := 0;
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vgaVSync <= '0';
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else
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if (vCounter = V_SYNC_END) then
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vgaVSync <= '1';
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end if;
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vCounter := vCounter + 1;
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end if;
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else
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if (hCounter = H_SYNC_END) then
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vgaHSync <= '1';
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end if;
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hCounter := hCounter + 1;
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end if;
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-- update blank
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if (vCounter >= 0 and
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vCounter < V_RES and
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hCounter >= 0 and
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hCounter < H_RES) then
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vgaBlank <= '1';
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else
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vgaBlank <= '0';
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end if;
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hCount <= conv_std_logic_vector(hCounter, 11);
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vCount <= conv_std_logic_vector(vCounter, 10);
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end if;
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end process;
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end Behavioral;
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