27 Commits
Author SHA1 Message Date
josh 4a39341a83 Turn off local APIC timer 2022-12-14 23:56:11 -05:00
josh 42ab6f396d Processing multiple RTC interrupts 2022-12-14 23:51:35 -05:00
josh 58d685a15b Program I/O APIC; got one RTC interrupt 2022-12-14 23:43:26 -05:00
josh d49f9e32cd dev checkpoint 2022-12-14 19:40:22 -05:00
josh b1a8f8d348 Handle local APIC exceptions 2022-12-07 23:24:01 -05:00
josh 9b52ae58e8 Get local APIC timer ready to run 2022-12-07 23:13:51 -05:00
josh 5799f94efe Configure local APIC interrupt vectors 2022-12-06 22:06:57 -05:00
josh 400a7b22db Enable local APIC interrupts 2022-12-06 21:22:56 -05:00
josh 2bba0dfca4 Add hulk.mtrr module 2022-11-08 21:49:41 -05:00
josh edba40b2c6 Implement frame buffer double-buffering
This slowed down drawing to video in QEMU/VirtualBox but greatly sped up
doing so on real hardware (no longer reading from video memory).
Despite the speed-up, it is still quite slow though.
2022-11-08 06:19:03 -05:00
josh 55604468c8 Allocate framebuffer buffer1 in HELLO 2022-11-07 21:27:52 -05:00
josh 71c30fa932 Reclaim bootloader page table pages 2022-11-06 21:59:42 -05:00
josh b3fb599b25 Move EFER initialization to initialize_cpu() 2022-11-05 22:49:57 -04:00
josh d357aada75 Map HULK regions separately 2022-11-05 22:45:35 -04:00
josh 1fef8ada29 Define acpi structs as static 2022-11-05 22:26:21 -04:00
josh 5231930543 Clean up ApicRegister 2022-11-05 22:22:09 -04:00
josh 95b9e4558a Move hulk.writef buffer variables to stack
Previously ldc2 was emitting AVX/SSE instructions to initialize these
buffers.
2022-11-05 22:06:18 -04:00
josh 354555d7f1 Disable AVX and SSE instruction generation for HULK 2022-11-05 22:03:13 -04:00
josh 1b69810e8f Turn on OSXSAVE 2022-11-05 21:17:30 -04:00
josh 64190b04cb Add initialize_cpu() 2022-11-05 20:27:48 -04:00
josh d7b12c7896 Run qemu with maximum supported host CPU features 2022-11-05 20:15:30 -04:00
josh 11f922da33 Add write_cr0() 2022-11-05 19:58:10 -04:00
josh 59e084c234 Add cpuid1() and output bit enums 2022-11-04 19:28:34 -04:00
josh f21ee0d149 Add enums for a few CPU register bits 2022-11-04 00:08:40 -04:00
josh 2a7c783bba Add write_cr4() 2022-11-03 23:31:55 -04:00
josh 1f2a2bea48 Add xgetbv()/xsetbv() 2022-11-03 22:45:35 -04:00
josh 8eedf4e267 Switch klog buffer to ubyte array to move it to bss section 2022-11-03 16:34:03 -04:00
17 changed files with 707 additions and 165 deletions

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+29 -2
View File
@@ -105,7 +105,34 @@ hulk_env = env "hulk", use: %w[ldc2 x86_64-elf-gcc] do |env|
"fontgen" => fontgen_env.expand("^/fontgen"))
env["sources"] = glob("src/hulk/**/*.d")
env["sources"] << "^/src/hulk/kfont.d"
env["DFLAGS"] += %w[-mtriple=x86_64-unknown-elf --betterC -release -O3 --wi --enable-cross-module-inlining -code-model=large]
cpu_attrs = %w[
-avx
-avx2
-avx512bf16
-avx512bitalg
-avx512bw
-avx512cd
-avx512dq
-avx512er
-avx512f
-avx512ifma
-avx512pf
-avx512vbmi
-avx512vbmi2
-avx512vl
-avx512vnni
-avx512vp2intersect
-avx512vpopcntdq
-sse
-sse-unaligned-mem
-sse2
-sse3
-sse4.1
-sse4.2
-sse4a
-ssse3
]
env["DFLAGS"] += %W[-mtriple=x86_64-unknown-elf -mattr=#{cpu_attrs.join(",")} --betterC -release -O3 --wi --enable-cross-module-inlining -code-model=large]
env["D_IMPORT_PATH"] += %w[src]
env["D_IMPORT_PATH"] << env.expand("^/src")
env["LD"] = "x86_64-elf-gcc"
@@ -159,7 +186,7 @@ task "run", desc: "Run HOS in QEMU" do
Dir.mktmpdir do |tmpdir|
img = hello_env.expand("^/HOS.img")
FileUtils.cp(img, tmpdir)
sh %W[qemu-system-x86_64 -bios OVMF.fd -drive file=#{tmpdir}/HOS.img,format=raw -device qemu-xhci -device usb-tablet]
sh %W[qemu-system-x86_64 -cpu max -bios OVMF.fd -drive file=#{tmpdir}/HOS.img,format=raw -device qemu-xhci -device usb-tablet]
end
end
+22 -15
View File
@@ -143,7 +143,7 @@ private bool set_graphics_mode()
/**
* Walk the EFI memory map and translate it to the HULK bootinfo format.
*/
private void get_memory_map(ulong * bss_phys, ulong * stack_phys, ulong * physical_address_limit, UINTN * memory_map_key)
private void get_memory_map(ulong * physical_address_limit, UINTN * memory_map_key)
{
immutable static ubyte[] efi_to_hulk_memory_map_type = [
BootInfo.MemoryRegion.Type.Reserved, // EfiReservedMemoryType
@@ -181,6 +181,8 @@ private void get_memory_map(ulong * bss_phys, ulong * stack_phys, ulong * physic
size_t count;
bool found_bss;
bool found_stack;
bool found_fb_buffer1;
const(size_t) fb_size = (bootinfo().fb.stride * bootinfo().fb.height * 4u + PAGE_SIZE - 1u) & ~(PAGE_SIZE - 1u);
for (count = 0u; count < n_entries; count++)
{
if (count > bootinfo().memory_map.length)
@@ -212,7 +214,7 @@ private void get_memory_map(ulong * bss_phys, ulong * stack_phys, ulong * physic
(descriptor.Type == EfiConventionalMemory) &&
(bootinfo().memory_map[count].size >= hulk_bss_size()))
{
*bss_phys = bootinfo().memory_map[count].base;
bootinfo().bss_phys = bootinfo().memory_map[count].base;
bootinfo().memory_map[count].base += hulk_bss_size();
bootinfo().memory_map[count].size -= hulk_bss_size();
found_bss = true;
@@ -221,14 +223,23 @@ private void get_memory_map(ulong * bss_phys, ulong * stack_phys, ulong * physic
(descriptor.Type == EfiConventionalMemory) &&
(bootinfo().memory_map[count].size >= hulk_stack_size()))
{
*stack_phys = bootinfo().memory_map[count].base;
bootinfo().stack_phys = bootinfo().memory_map[count].base;
bootinfo().memory_map[count].base += hulk_stack_size();
bootinfo().memory_map[count].size -= hulk_stack_size();
found_stack = true;
}
if ((!found_fb_buffer1) &&
(descriptor.Type == EfiConventionalMemory) &&
(bootinfo().memory_map[count].size >= fb_size))
{
bootinfo().fb_buffer1_phys = bootinfo().memory_map[count].base;
bootinfo().memory_map[count].base += fb_size;
bootinfo().memory_map[count].size -= fb_size;
found_fb_buffer1 = true;
}
}
bootinfo().memory_map_count = count;
if ((!found_bss) || (!found_stack))
if ((!found_bss) || (!found_stack) || (!found_fb_buffer1))
{
for (;;) {}
}
@@ -379,7 +390,7 @@ private bool map2m(ulong source_page, ulong dest_page, PageTable * pt_base)
*
* @param pt_base Page table base address.
*/
private bool map_hulk(PageTable * pt_base, ulong bss_phys, ulong stack_phys)
private bool map_hulk(PageTable * pt_base)
{
/* Map HULK bin region. */
ulong virt = hulk_virt_base_address();
@@ -389,13 +400,13 @@ private bool map_hulk(PageTable * pt_base, ulong bss_phys, ulong stack_phys)
}
/* Map HULK bss region. */
virt += hulk_bin_size();
if (!map4kregion(virt, bss_phys, hulk_bss_size(), pt_base))
if (!map4kregion(virt, bootinfo().bss_phys, hulk_bss_size(), pt_base))
{
return false;
}
/* Map HULK stack. */
virt = hulk_virt_stack_top() - hulk_stack_size();
if (!map4kregion(virt, stack_phys, hulk_stack_size(), pt_base))
if (!map4kregion(virt, bootinfo().stack_phys, hulk_stack_size(), pt_base))
{
return false;
}
@@ -407,7 +418,7 @@ private bool map_hulk(PageTable * pt_base, ulong bss_phys, ulong stack_phys)
*
* @param physical_address_limit Maximum physical address to identity map.
*/
private bool build_page_tables(ulong physical_address_limit, ulong bss_phys, ulong stack_phys)
private bool build_page_tables(ulong physical_address_limit)
{
PageTable * pt_base = new_page_table();
if (pt_base == null)
@@ -443,7 +454,7 @@ private bool build_page_tables(ulong physical_address_limit, ulong bss_phys, ulo
return false;
}
/* Map HULK regions. */
if (!map_hulk(pt_base, bss_phys, stack_phys))
if (!map_hulk(pt_base))
{
return false;
}
@@ -518,13 +529,11 @@ extern (C) EFI_STATUS efi_main(EFI_HANDLE image_handle, EFI_SYSTEM_TABLE * st)
return EFI_SUCCESS;
}
ulong bss_phys;
ulong stack_phys;
ulong physical_address_limit;
UINTN memory_map_key;
for (;;)
{
get_memory_map(&bss_phys, &stack_phys, &physical_address_limit, &memory_map_key);
get_memory_map(&physical_address_limit, &memory_map_key);
EFI_STATUS status = st.BootServices.ExitBootServices(image_handle, memory_map_key);
if (status == EFI_INVALID_PARAMETER)
@@ -540,14 +549,12 @@ extern (C) EFI_STATUS efi_main(EFI_HANDLE image_handle, EFI_SYSTEM_TABLE * st)
return EFI_SUCCESS;
}
if (!build_page_tables(physical_address_limit, bss_phys, stack_phys))
if (!build_page_tables(physical_address_limit))
{
return EFI_SUCCESS;
}
bootinfo().hulk_phys = hulk_bin_phys();
bootinfo().bss_phys = bss_phys;
bootinfo().stack_phys = stack_phys;
jump_to_hulk();
+5 -5
View File
@@ -12,7 +12,7 @@ struct acpi
enum uint APIC_SIGNATURE = 0x43495041u;
enum uint XSDT_SIGNATURE = 0x54445358u;
struct XsdtHeader
static struct XsdtHeader
{
uint signature;
uint length;
@@ -23,16 +23,16 @@ struct acpi
uint oem_revision;
uint creator_id;
uint creator_revision;
};
}
struct Xsdt
static struct Xsdt
{
XsdtHeader header;
uint _pad;
ulong[0] tables;
}
struct MadtHeader
static struct MadtHeader
{
uint signature;
uint length;
@@ -47,7 +47,7 @@ struct acpi
uint flags;
}
struct MadtEntry
static struct MadtEntry
{
ubyte type;
ubyte length;
+52 -17
View File
@@ -6,24 +6,19 @@ module hulk.apic;
import hulk.klog;
import hulk.hurl;
import hulk.acpi;
import hulk.idt;
struct apic
{
private enum uint PERIODIC_MODE = 0x2_0000u;
static struct ApicRegister
{
private uint register;
public uint value;
alias value this;
private ubyte[12] _padding;
public uint read() const
{
return register;
}
public void write(uint value)
{
register = value;
}
};
}
static struct ApicRegisters
{
@@ -55,15 +50,55 @@ struct apic
ApicRegister current_count;
ApicRegister[4] _reserved3;
ApicRegister divide_configuration;
};
}
static struct IoApicRegisters
{
ApicRegister address;
ApicRegister data;
}
private static __gshared ApicRegisters * apic_registers;
private static __gshared IoApicRegisters * io_apic_registers;
public static void initialize()
{
ApicRegisters * apic_registers =
cast(ApicRegisters *)acpi.apic_address;
apic_registers = cast(ApicRegisters *)acpi.apic_address;
io_apic_registers = cast(IoApicRegisters *)0xFEC0_0000u;
hurl.map(cast(ulong)apic_registers, cast(ulong)apic_registers,
PT_WRITABLE | PT_WRITE_THROUGH | PT_DISABLE_CACHE | PT_NO_EXECUTE);
klog.writefln("LAPIC ID: 0x%08x", apic_registers.lapic_id.read());
klog.writefln("LAPIC version: 0x%08x", apic_registers.lapic_version.read());
hurl.map(cast(ulong)io_apic_registers, cast(ulong)io_apic_registers,
PT_WRITABLE | PT_WRITE_THROUGH | PT_DISABLE_CACHE | PT_NO_EXECUTE);
klog.writefln("LAPIC ID: 0x%08x", apic_registers.lapic_id.value);
klog.writefln("LAPIC version: 0x%08x", apic_registers.lapic_version.value);
/* Enable local APIC to receive interrupts and set spurious interrupt
* vector to 0xFF. */
apic_registers.spurious_interrupt_vector.value = 0x1FFu;
// apic_registers.lvt_timer.value = idt.INT_LAPIC_TIMER | PERIODIC_MODE;
apic_registers.lvt_timer.value = idt.INT_LAPIC_TIMER;
apic_registers.lvt_lint[0].value = idt.INT_LAPIC_LINT0;
apic_registers.lvt_lint[1].value = idt.INT_LAPIC_LINT1;
// apic_registers.divide_configuration.value = 3u;
configure_io_apic_irq(8u, 0x48u);
}
private static void configure_io_apic_irq(size_t io_apic_irq, size_t interrupt_id)
{
ulong entry = interrupt_id;
io_apic_registers.address.value = cast(uint)(0x10u + io_apic_irq * 2u);
io_apic_registers.data.value = entry & 0xFFFF_FFFFu;
io_apic_registers.address.value = cast(uint)(0x10u + io_apic_irq * 2u + 1u);
io_apic_registers.data.value = entry >> 32u;
}
public static void eoi()
{
apic_registers.eoi.value = 0u;
}
public static void isr(ulong vector)
{
klog.writefln("APIC ISR 0x%x", vector);
eoi();
}
}
+3
View File
@@ -69,6 +69,9 @@ struct BootInfo
/* Physical address of stack while jumping to HULK. */
ulong stack_phys;
/* Physical address of framebuffer buffer1. */
ulong fb_buffer1_phys;
/* Physical address of ACPI XSDT table. */
ulong acpi_xsdt_phys;
}
+143
View File
@@ -5,6 +5,57 @@ module hulk.cpu;
import ldc.llvmasm;
/** CR0 bits. @{ */
enum ulong CR0_PE = 0x1u;
enum ulong CR0_MP = 0x2u;
enum ulong CR0_EM = 0x4u;
enum ulong CR0_TS = 0x8u;
enum ulong CR0_ET = 0x10u;
enum ulong CR0_NE = 0x20u;
enum ulong CR0_WP = 0x1_0000u;
enum ulong CR0_AM = 0x4_0000u;
enum ulong CR0_NW = 0x2000_0000u;
enum ulong CR0_CD = 0x4000_0000u;
enum ulong CR0_PG = 0x8000_0000u;
/** @} */
/** CR4 bits. @{ */
enum ulong CR4_VME = 0x1u;
enum ulong CR4_PVI = 0x2u;
enum ulong CR4_TSD = 0x4u;
enum ulong CR4_DE = 0x8u;
enum ulong CR4_PSE = 0x10u;
enum ulong CR4_PAE = 0x20u;
enum ulong CR4_MCE = 0x40u;
enum ulong CR4_PGE = 0x80u;
enum ulong CR4_PCE = 0x100u;
enum ulong CR4_OSFXSR = 0x200u;
enum ulong CR4_OSXMMEXCPT = 0x400u;
enum ulong CR4_UMIP = 0x800u;
enum ulong CR4_VMXE = 0x2000u;
enum ulong CR4_SMXE = 0x4000u;
enum ulong CR4_FSGSBASE = 0x1_0000u;
enum ulong CR4_PCIDE = 0x2_0000u;
enum ulong CR4_OSXSAVE = 0x4_0000u;
enum ulong CR4_SMEP = 0x10_0000u;
enum ulong CR4_SMAP = 0x20_0000u;
enum ulong CR4_PKE = 0x40_0000u;
enum ulong CR4_CET = 0x80_0000u;
enum ulong CR4_PKS = 0x100_0000u;
/** @} */
/** XCR0 bits. @{ */
enum ulong XCR0_X87 = 0x1u;
enum ulong XCR0_SSE = 0x2u;
enum ulong XCR0_AVX = 0x4u;
enum ulong XCR0_BNDREG = 0x8u;
enum ulong XCR0_BNDSCR = 0x10u;
enum ulong XCR0_OPMASK = 0x20u;
enum ulong XCR0_ZMM_HI256 = 0x40u;
enum ulong XCR0_HI16_ZMM = 0x80u;
enum ulong XCR0_PKRU = 0x100u;
/** @} */
/** MSR register numbers. @{ */
enum uint MSR_EFER = 0xC000_0080u;
/** @} */
@@ -20,6 +71,70 @@ enum uint EFER_FFXSR = 0x4000u;
enum uint EFER_TCE = 0x8000u;
/** @} */
/** CPUID 1 bits. @{ */
enum uint CPUID_1_EDX_FPU = 0x1u;
enum uint CPUID_1_EDX_VME = 0x2u;
enum uint CPUID_1_EDX_DE = 0x4u;
enum uint CPUID_1_EDX_PSE = 0x8u;
enum uint CPUID_1_EDX_TSC = 0x10u;
enum uint CPUID_1_EDX_MSR = 0x20u;
enum uint CPUID_1_EDX_PAE = 0x40u;
enum uint CPUID_1_EDX_MCE = 0x80u;
enum uint CPUID_1_EDX_CX8 = 0x100u;
enum uint CPUID_1_EDX_APIC = 0x200u;
enum uint CPUID_1_EDX_SEP = 0x800u;
enum uint CPUID_1_EDX_MTRR = 0x1000u;
enum uint CPUID_1_EDX_PGE = 0x2000u;
enum uint CPUID_1_EDX_MCA = 0x4000u;
enum uint CPUID_1_EDX_CMOV = 0x8000u;
enum uint CPUID_1_EDX_PAT = 0x1_0000u;
enum uint CPUID_1_EDX_PSE36 = 0x2_0000u;
enum uint CPUID_1_EDX_PSN = 0x4_0000u;
enum uint CPUID_1_EDX_CLFSH = 0x8_0000u;
enum uint CPUID_1_EDX_DS = 0x20_0000u;
enum uint CPUID_1_EDX_ACPI = 0x40_0000u;
enum uint CPUID_1_EDX_MMX = 0x80_0000u;
enum uint CPUID_1_EDX_FXSR = 0x100_0000u;
enum uint CPUID_1_EDX_SSE = 0x200_0000u;
enum uint CPUID_1_EDX_SSE2 = 0x400_0000u;
enum uint CPUID_1_EDX_SS = 0x800_0000u;
enum uint CPUID_1_EDX_HTT = 0x1000_0000u;
enum uint CPUID_1_EDX_TM = 0x2000_0000u;
enum uint CPUID_1_EDX_IA64 = 0x4000_0000u;
enum uint CPUID_1_EDX_PBE = 0x8000_0000u;
enum uint CPUID_1_ECX_SSE3 = 0x1u;
enum uint CPUID_1_ECX_PCLMULQDQ = 0x2u;
enum uint CPUID_1_ECX_DTES64 = 0x4u;
enum uint CPUID_1_ECX_MONITOR = 0x8u;
enum uint CPUID_1_ECX_DSCPL = 0x10u;
enum uint CPUID_1_ECX_VMX = 0x20u;
enum uint CPUID_1_ECX_SMX = 0x40u;
enum uint CPUID_1_ECX_EST = 0x80u;
enum uint CPUID_1_ECX_TM2 = 0x100u;
enum uint CPUID_1_ECX_SSSE3 = 0x200u;
enum uint CPUID_1_ECX_CNXTID = 0x400u;
enum uint CPUID_1_ECX_SDBG = 0x800u;
enum uint CPUID_1_ECX_FMA = 0x1000u;
enum uint CPUID_1_ECX_CX16 = 0x2000u;
enum uint CPUID_1_ECX_XTPR = 0x4000u;
enum uint CPUID_1_ECX_PDCM = 0x8000u;
enum uint CPUID_1_ECX_PCID = 0x2_0000u;
enum uint CPUID_1_ECX_DCA = 0x4_0000u;
enum uint CPUID_1_ECX_SSE41 = 0x8_0000u;
enum uint CPUID_1_ECX_SSE42 = 0x10_0000u;
enum uint CPUID_1_ECX_X2APIC = 0x20_0000u;
enum uint CPUID_1_ECX_MOVBE = 0x40_0000u;
enum uint CPUID_1_ECX_POPCNT = 0x80_0000u;
enum uint CPUID_1_ECX_TSCDEADLINE = 0x100_0000u;
enum uint CPUID_1_ECX_AES = 0x200_0000u;
enum uint CPUID_1_ECX_XSAVE = 0x400_0000u;
enum uint CPUID_1_ECX_OSXSAVE = 0x800_0000u;
enum uint CPUID_1_ECX_AVX = 0x1000_0000u;
enum uint CPUID_1_ECX_F16C = 0x2000_0000u;
enum uint CPUID_1_ECX_RDRND = 0x4000_0000u;
enum uint CPUID_1_ECX_HYPERVISOR = 0x8000_0000u;
/** @} */
void cli()
{
__asm("cli", "");
@@ -40,6 +155,11 @@ ulong read_cr0()
return __asm!ulong("mov %cr0, %rax", "={rax}");
}
void write_cr0(ulong v)
{
__asm("mov $0, %cr0", "r", v);
}
ulong read_cr2()
{
return __asm!ulong("mov %cr2, %rax", "={rax}");
@@ -60,6 +180,11 @@ ulong read_cr4()
return __asm!ulong("mov %cr4, %rax", "={rax}");
}
void write_cr4(ulong v)
{
__asm("mov $0, %cr4", "r", v);
}
ulong rdmsr(uint msr)
{
return __asm!ulong(`
@@ -73,6 +198,19 @@ void wrmsr(uint msr, ulong value)
__asm(`wrmsr`, "{ecx},{edx},{eax}", msr, value >> 32u, value);
}
ulong xgetbv(uint xcr)
{
return __asm!ulong(`
xgetbv
shl $$32, %rdx
or %rdx, %rax`, "={rax},{ecx},~{rdx}", xcr);
}
void xsetbv(uint xcr, ulong value)
{
__asm(`xsetbv`, "{ecx},{edx},{eax}", xcr, value >> 32u, value);
}
ubyte in8(ushort ioaddr)
{
return __asm!ubyte("inb %dx, %al", "={al},{dx}", ioaddr);
@@ -102,3 +240,8 @@ void out32(ushort ioaddr, ulong v)
{
__asm("outl %eax, %dx", "{dx},{eax}", ioaddr, v);
}
void cpuid1(uint * ebx, uint * ecx, uint * edx)
{
__asm("cpuid", "=*{ebx},=*{ecx},=*{edx},{eax}", ebx, ecx, edx, 1u);
}
+34 -16
View File
@@ -13,8 +13,11 @@ import hulk.kfont;
*/
struct fb
{
/** Frame buffer base address. */
private __gshared static uint * m_buffer;
/** Device frame buffer base address. */
private __gshared static uint * m_device_buffer;
/** Frame buffer 1 base address. */
private __gshared static uint * m_buffer1;
/** Frame buffer width. */
private __gshared static uint m_width;
@@ -47,14 +50,16 @@ struct fb
/**
* Initialize a frame buffer.
*
* @param buffer Frame buffer base address.
* @param device_buffer Device frame buffer base address.
* @param buffer1 Frame buffer 1 base address.
* @param width Frame buffer width.
* @param height Frame buffer height.
* @param stride Frame buffer stride.
*/
static void initialize(uint * buffer, uint width, uint height, uint stride)
static void initialize(uint * device_buffer, uint * buffer1, uint width, uint height, uint stride)
{
m_buffer = buffer;
m_device_buffer = device_buffer;
m_buffer1 = buffer1;
m_width = width;
m_height = height;
m_stride = stride;
@@ -68,7 +73,8 @@ struct fb
*/
static void clear(uint color = 0u)
{
memset32(m_buffer, color, m_buffer_size);
memset32(m_buffer1, color, m_buffer_size);
memset32(m_device_buffer, color, m_buffer_size);
}
/**
@@ -85,7 +91,8 @@ struct fb
for (size_t iy = 0u; iy < height; iy++)
{
size_t buffer_index = buffer_index(x, y);
memset32(&m_buffer[buffer_index], color, width);
memset32(&m_buffer1[buffer_index], color, width);
memset32(&m_device_buffer[buffer_index], color, width);
y++;
}
}
@@ -101,7 +108,8 @@ struct fb
static void hline(size_t x, size_t y, size_t width, uint color)
{
size_t buffer_index = buffer_index(x, y);
memset32(&m_buffer[buffer_index], color, width);
memset32(&m_buffer1[buffer_index], color, width);
memset32(&m_device_buffer[buffer_index], color, width);
}
/**
@@ -117,7 +125,8 @@ struct fb
size_t buffer_index = buffer_index(x, y);
for (size_t iy = 0u; iy < height; iy++)
{
m_buffer[buffer_index] = color;
m_buffer1[buffer_index] = color;
m_device_buffer[buffer_index] = color;
buffer_index -= m_stride;
}
}
@@ -153,17 +162,19 @@ struct fb
size_t bitmap_index;
for (size_t iy = 0u; iy < height; iy++)
{
size_t row_buffer_index = buffer_index(x, y);
for (size_t ix = 0u; ix < width; ix++)
{
size_t buffer_index = buffer_index(x + ix, y);
size_t buffer_index = row_buffer_index + ix;
ubyte alpha = alpha_bitmap[bitmap_index];
uint current_color = m_buffer[buffer_index];
uint current_color = m_buffer1[buffer_index];
uint in_color_scaled = scale_color(color, alpha);
uint old_color_scaled = scale_color(current_color, 255u - alpha);
uint new_color = old_color_scaled + in_color_scaled;
m_buffer[buffer_index] = new_color;
m_buffer1[buffer_index] = new_color;
bitmap_index++;
}
memcpy32(&m_device_buffer[row_buffer_index], &m_buffer1[row_buffer_index], width);
y--;
}
}
@@ -202,13 +213,15 @@ struct fb
size_t bitmap_index;
for (size_t iy = 0u; iy < height; iy++)
{
size_t row_buffer_index = buffer_index(x, y);
for (size_t ix = 0u; ix < width; ix++)
{
size_t buffer_index = buffer_index(x + ix, y);
size_t buffer_index = row_buffer_index + ix;
ubyte alpha = alpha_bitmap[bitmap_index];
m_buffer[buffer_index] = (alpha << 16u) | (alpha << 8u) | alpha;
m_buffer1[buffer_index] = (alpha << 16u) | (alpha << 8u) | alpha;
bitmap_index++;
}
memcpy32(&m_device_buffer[row_buffer_index], &m_buffer1[row_buffer_index], width);
y--;
}
}
@@ -239,9 +252,14 @@ struct fb
*/
static void copy_rows_up(size_t y, size_t height, size_t offset)
{
memcpy32(&m_buffer[buffer_index(0u, y + height + offset - 1u)],
&m_buffer[buffer_index(0u, y + height - 1u)],
size_t dest_buffer_index = buffer_index(0u, y + height + offset - 1u);
size_t src_buffer_index = buffer_index(0u, y + height - 1u);
memcpy32(&m_buffer1[dest_buffer_index],
&m_buffer1[src_buffer_index],
(m_stride * height));
memcpy32(&m_device_buffer[dest_buffer_index],
&m_buffer1[dest_buffer_index],
(m_stride * height));
}
/**
+20 -82
View File
@@ -1,20 +1,18 @@
/**
* HIPPO, the HOS In-place Physical Page Organizer.
*
* HIPPO maintains a list of free physical pages "in place", meaning that the
* available page itself is used as the linked list entry so separate memory
* is not needed to keep track of the available pages.
*/
module hulk.hippo;
import hulk.header;
import hulk.bootinfo;
import hulk.klog;
import hulk.linker_addresses;
import hulk.pagetable;
struct hippo
{
/**
* Linked list node entry for a physical page.
*/
private struct PhysicalPage
private static struct PhysicalPage
{
PhysicalPage * next;
}
@@ -27,96 +25,25 @@ struct hippo
/**
* Number of free physical pages.
*/
private static __gshared size_t n_free_pages;
/**
* Physical address limit.
*/
public static __gshared size_t physical_address_limit;
/**
* Initialize HIPPO.
*
* Ok, what we do here is iterate through all of the memory map regions in
* the bootinfo memory_map array, and create a linked list of all free
* physical pages that are available. Within the available memory regions,
* we have to watch out for the following items:
* 1) HULK binary (text + data)
* - This includes the HULK header and bootinfo structures
* 2) HULK bss
* 3) HULK stack
* 4) Framebuffer
* 5) Page tables
*
* @param bootinfo HULK boot information structure.
*/
public static void initialize(HulkHeader * header)
{
size_t usable_memory;
ulong[2][4] reserved = [
[header.bootinfo.hulk_phys, LinkerAddresses.hulk_binary_size],
[header.bootinfo.bss_phys, LinkerAddresses.hulk_bss_size],
[header.bootinfo.stack_phys, header.stack_size],
[cast(ulong)header.bootinfo.fb.buffer, header.bootinfo.fb.height * header.bootinfo.fb.stride * 4u],
];
for (size_t ri = 0u; ri < reserved.length; ri++)
{
reserved[ri][1] += reserved[ri][0];
}
for (size_t bii = 0u; bii < header.bootinfo.memory_map_count; bii++)
{
if ((header.bootinfo.memory_map[bii].type == BootInfo.MemoryRegion.Type.Bootloader) ||
(header.bootinfo.memory_map[bii].type == BootInfo.MemoryRegion.Type.Conventional))
{
ulong phys = header.bootinfo.memory_map[bii].base;
ulong phys_end = phys + header.bootinfo.memory_map[bii].size;
if (phys_end > physical_address_limit)
{
physical_address_limit = phys_end;
}
usable_memory += header.bootinfo.memory_map[bii].size;
while (phys < phys_end)
{
bool is_reserved = false;
for (size_t ri = 0u; ri < reserved.length; ri++)
{
if ((reserved[ri][0] <= phys) && (phys < reserved[ri][1]))
{
is_reserved = true;
break;
}
}
if (!is_reserved)
{
free_page(phys);
}
phys += PAGE_SIZE;
}
}
}
size_t usable_kb = usable_memory >> 10u;
size_t usable_mb = usable_kb >> 10u;
size_t frac_mb = ((1000u * (usable_kb & 0x3FFu)) + 512u) >> 10u;
klog.writefln("Found %u.%03uMB of usable RAM", usable_mb, frac_mb);
}
private static __gshared size_t m_n_free_pages;
/**
* Free a physical page.
*
* @param phys Physical page address.
*/
private static void free_page(ulong phys)
public static void free_page(T)(T phys)
{
PhysicalPage * pp = cast(PhysicalPage *)phys;
pp.next = free_pages;
free_pages = pp;
n_free_pages++;
m_n_free_pages++;
}
/**
* Allocate a physical page.
*
* @return Page address, or null if none available.
* @return Page address, or null if no pages are available.
*/
public static void * allocate_page()
{
@@ -125,7 +52,18 @@ struct hippo
{
pp = free_pages;
free_pages = free_pages.next;
m_n_free_pages--;
}
return cast(void *)pp;
}
/**
* Get the number of free pages.
*
* @return The number of free pages.
*/
public @property size_t n_free_pages() const
{
return m_n_free_pages;
}
}
+25 -2
View File
@@ -20,6 +20,8 @@ import ldc.llvmasm;
import hulk.pic;
import hulk.acpi;
import hulk.apic;
import hulk.rtc;
import hulk.pit;
extern extern(C) __gshared ubyte _hulk_bss_size;
@@ -33,27 +35,48 @@ private __gshared HulkHeader hulk_header = {
HULK_VIRTUAL_FRAMEBUFFER_ADDRESS, /* virt_fb_buffer */
};
private void initialize_cpu()
{
/* Enable SSE. */
/* Turn off CR0.EM and turn on CR0.MP. */
write_cr0((read_cr0() & ~CR0_EM) | CR0_MP);
/* Set CR4.OSFXSR and CR4.OSXMMEXCPT. */
write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT);
/* Enable OSXSAVE. */
write_cr4(read_cr4() | CR4_OSXSAVE);
/* Turn on NXE (no execute enable) flag in the EFER MSR. */
wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE);
}
/**
* HULK entry point.
*/
void hulk_start()
{
cli();
initialize_cpu();
gdt.initialize();
idt.initialize();
fb.initialize(cast(uint *)HULK_VIRTUAL_FRAMEBUFFER_ADDRESS, hulk_header.bootinfo.fb.width, hulk_header.bootinfo.fb.height, hulk_header.bootinfo.fb.stride);
fb.initialize(cast(uint *)HULK_VIRTUAL_FRAMEBUFFER_ADDRESS,
cast(uint *)hulk_header.bootinfo.fb_buffer1_phys,
hulk_header.bootinfo.fb.width,
hulk_header.bootinfo.fb.height,
hulk_header.bootinfo.fb.stride);
console.initialize();
console.clear();
klog.initialize();
klog.writefln("Welcome to HULK, the HOS UltraLight Kernel!");
hippo.initialize(&hulk_header);
hurl.initialize(&hulk_header);
pci.initialize();
pic.initialize();
acpi.initialize(hulk_header.bootinfo.acpi_xsdt_phys);
apic.initialize();
rtc.initialize();
pit.initialize();
sti();
for (;;)
+168 -16
View File
@@ -10,6 +10,7 @@ import hulk.cpu;
import hulk.hippo;
import hulk.memory;
import hulk.klog;
import hulk.bootinfo;
import hulk.header;
import hulk.linker_addresses;
@@ -24,31 +25,56 @@ enum ulong HULK_VIRTUAL_FRAMEBUFFER_ADDRESS = 0xFFFF_A000_0000_0000u;
struct hurl
{
/**
* Pointer to the base page table.
*/
private static __gshared PageTable * m_pt_base;
/**
* Initialize HURL.
* Build HULK page tables.
*
* @param bootinfo HULK boot information structure.
* @param physical_address_limit
* Limit of physical memory.
*/
public static void initialize(HulkHeader * header)
private static void build_page_tables(HulkHeader * header, size_t physical_address_limit)
{
/* Turn on NXE (no execute enable) flag in the EFER MSR. */
wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE);
m_pt_base = allocate_pt();
size_t hulk_binary_size = LinkerAddresses.hulk_binary_size;
/* Identity map all physical RAM. */
map_range(0u,
0u,
hippo.physical_address_limit,
physical_address_limit,
PT_WRITABLE | PT_NO_EXECUTE);
/* Map HULK binary region. */
map_range(HULK_VIRTUAL_BASE_ADDRESS,
header.bootinfo.hulk_phys,
hulk_binary_size,
PT_WRITABLE);
ulong phys_address = header.bootinfo.hulk_phys;
ulong virt_address = HULK_VIRTUAL_BASE_ADDRESS;
/* Map HULK header region. */
map_range(virt_address,
phys_address,
LinkerAddresses.hulk_header_size,
PT_NO_EXECUTE);
phys_address += LinkerAddresses.hulk_header_size;
virt_address += LinkerAddresses.hulk_header_size;
/* Map HULK text region. */
map_range(virt_address,
phys_address,
LinkerAddresses.hulk_text_size,
0u);
phys_address += LinkerAddresses.hulk_text_size;
virt_address += LinkerAddresses.hulk_text_size;
/* Map HULK rodata region. */
map_range(virt_address,
phys_address,
LinkerAddresses.hulk_rodata_size,
PT_NO_EXECUTE);
phys_address += LinkerAddresses.hulk_rodata_size;
virt_address += LinkerAddresses.hulk_rodata_size;
/* Map HULK data region. */
map_range(virt_address,
phys_address,
LinkerAddresses.hulk_data_size,
PT_WRITABLE | PT_NO_EXECUTE);
virt_address += LinkerAddresses.hulk_data_size;
/* Map HULK BSS region. */
map_range(HULK_VIRTUAL_BASE_ADDRESS + hulk_binary_size,
map_range(virt_address,
header.bootinfo.bss_phys,
LinkerAddresses.hulk_bss_size,
PT_WRITABLE | PT_NO_EXECUTE);
@@ -57,15 +83,141 @@ struct hurl
header.bootinfo.stack_phys,
header.stack_size,
PT_WRITABLE | PT_NO_EXECUTE);
/* Map HULK framebuffer. */
/* Map device framebuffer. */
map_range(HULK_VIRTUAL_FRAMEBUFFER_ADDRESS,
cast(ulong)header.bootinfo.fb.buffer,
header.bootinfo.fb.height * header.bootinfo.fb.stride * 4u,
PT_WRITABLE | PT_NO_EXECUTE);
/* Map framebuffer buffer1. */
map_range(cast(ulong)header.bootinfo.fb_buffer1_phys,
cast(ulong)header.bootinfo.fb_buffer1_phys,
header.bootinfo.fb.height * header.bootinfo.fb.stride * 4u,
PT_WRITABLE | PT_NO_EXECUTE);
write_cr3(cast(ulong)m_pt_base);
}
public static void map(ulong virtual, ulong physical, ulong flags)
/**
* Reclaim the pages that were used for the bootloader page tables.
*
* @param pt
* The page table to reclaim pages from.
* @param level
* Page table level (internally used while recursing the page tables).
*
* @return Number of pages reclaimed.
*/
private static size_t reclaim_bootloader_page_table_pages(PageTable * pt, size_t level = 0u)
{
map(pt, pt, PT_WRITABLE | PT_NO_EXECUTE);
size_t reclaimed_pages;
for (size_t i = 0u; i < PageTable.N_ENTRIES; i++)
{
PageTableEntry pte = (*pt)[i];
if (pte.present && (level < 2u) && !pte.huge)
{
/* For the first two levels of page tables, first
* recurse and free pages from the lower level page
* tables before reclaiming this entry. */
reclaimed_pages += reclaim_bootloader_page_table_pages(pte.follow(), level + 1u);
}
}
hippo.free_page(pt);
reclaimed_pages++;
return reclaimed_pages;
}
/**
* Initialize HURL.
*
* @param bootinfo HULK boot information structure.
*/
public static void initialize(HulkHeader * header)
{
PageTable * bootloader_pt_base = cast(PageTable *)read_cr3();
/*
* Ok, what we do here is iterate through all of the memory map regions
* in the bootinfo memory_map array and mark each page that is not in
* use in a reserved range as available. Within the available memory
* regions, we have to watch out for the following items:
* 1) HULK binary (header + text + rodata + data)
* 2) Framebuffer
* In addition to these ranges, there are also pages for the following
* purposes that are not represented in the memory map from the
* bootloader:
* 3) HULK BSS
* 4) HULK stack
* 5) bootloader page table pages
* 6) framebuffer buffer1
*/
size_t usable_memory;
size_t physical_address_limit;
const(size_t) fb_size = (header.bootinfo.fb.height * header.bootinfo.fb.stride * 4u + PAGE_SIZE - 1u) & ~(PAGE_SIZE - 1u);
ulong[2][2] reserved = [
[header.bootinfo.hulk_phys, LinkerAddresses.hulk_binary_size],
[cast(ulong)header.bootinfo.fb.buffer, fb_size],
];
for (size_t ri = 0u; ri < reserved.length; ri++)
{
reserved[ri][1] += reserved[ri][0];
}
for (size_t bii = 0u; bii < header.bootinfo.memory_map_count; bii++)
{
if ((header.bootinfo.memory_map[bii].type == BootInfo.MemoryRegion.Type.Bootloader) ||
(header.bootinfo.memory_map[bii].type == BootInfo.MemoryRegion.Type.Conventional))
{
ulong phys = header.bootinfo.memory_map[bii].base;
ulong phys_end = phys + header.bootinfo.memory_map[bii].size;
if (phys_end > physical_address_limit)
{
physical_address_limit = phys_end;
}
usable_memory += header.bootinfo.memory_map[bii].size;
while (phys < phys_end)
{
bool is_reserved = false;
for (size_t ri = 0u; ri < reserved.length; ri++)
{
if ((reserved[ri][0] <= phys) && (phys < reserved[ri][1]))
{
is_reserved = true;
break;
}
}
if (!is_reserved)
{
hippo.free_page(phys);
}
phys += PAGE_SIZE;
}
}
}
/*
* Now that we have available physical pages to allocate from, we can
* build new page tables to replace the bootloader page tables.
*/
build_page_tables(header, physical_address_limit);
/*
* After we have switched to the newly constructed page tables, we can
* iterate through and free the bootloader page tables. They are most
* likely already mapped because we just identity mapped every page up
* to the physical_address_limit determined above. But just in case the
* bootloader used the last pages of RAM for the page table pages, we
* will make sure to map them as we traverse them.
*/
size_t reclaimed_bootloader_page_table_memory = reclaim_bootloader_page_table_pages(bootloader_pt_base) << 10u;
usable_memory += reclaimed_bootloader_page_table_memory;
usable_memory += LinkerAddresses.hulk_bss_size;
usable_memory += header.stack_size;
usable_memory += fb_size;
klog.writefln("Usable memory: %uKB", usable_memory >> 10u);
klog.writefln("Kernel size: %uKB", (LinkerAddresses.hulk_binary_size + LinkerAddresses.hulk_bss_size + header.stack_size) >> 10u);
}
public static void map(T, U)(T virtual, U physical, ulong flags)
{
PageTable * pt = m_pt_base;
for (size_t level = 0; level < 4u; level++)
@@ -87,7 +239,7 @@ struct hurl
}
else
{
*ppte = PageTableEntry(physical, flags | PT_PRESENT);
*ppte = PageTableEntry(cast(ulong)physical, flags | PT_PRESENT);
}
}
}
+29 -6
View File
@@ -8,9 +8,18 @@ import ldc.llvmasm;
import hulk.fb;
import hulk.console;
import hulk.klog;
import hulk.apic;
import hulk.rtc;
struct idt
{
/* The I/O APIC is configured to map IRQ 0 to interrupt 64 (0x40). */
public static enum ulong INT_RTC = 0x48u; /* IRQ 8 */
public static enum ulong INT_LAPIC_TIMER = 0x70u;
public static enum ulong INT_LAPIC_LINT0 = 0x71u;
public static enum ulong INT_LAPIC_LINT1 = 0x72u;
struct idtr_t
{
ushort limit;
@@ -94,12 +103,26 @@ struct idt
public extern(C) void isr(ulong vector, ulong arg)
{
console.clear();
fb.clear(0xFF8000u);
klog.writefln("ISR %u, 0x%x", vector, arg);
__asm("cli", "");
for (;;)
switch (vector)
{
__asm("hlt", "");
case idt.INT_RTC:
rtc.isr();
break;
case idt.INT_LAPIC_TIMER:
case idt.INT_LAPIC_LINT0:
case idt.INT_LAPIC_LINT1:
apic.isr(vector);
break;
default:
console.clear();
fb.clear(0xFF8000u);
klog.writefln("ISR %u, 0x%x", vector, arg);
__asm("cli", "");
for (;;)
{
__asm("hlt", "");
}
}
}
+1 -1
View File
@@ -19,7 +19,7 @@ struct klog
private enum size_t KLOG_SIZE = 1u << KLOG_SIZE_LOG;
/** Kernel log buffer. */
private static __gshared align(4096) char[KLOG_SIZE] klog_buffer;
private static __gshared align(4096) ubyte[KLOG_SIZE] klog_buffer;
/** Write index in the kernel log buffer. */
private static __gshared size_t klog_index;
+70
View File
@@ -0,0 +1,70 @@
/**
* MTRR (Memory Type Range Register) support for HULK.
*/
module hulk.mtrr;
import hulk.cpu;
import hulk.klog;
enum ulong MTRR_TYPE_UC = 0u; /* Uncacheable */
enum ulong MTRR_TYPE_WC = 1u; /* Write-Combining */
enum ulong MTRR_TYPE_WT = 4u; /* Writethrough */
enum ulong MTRR_TYPE_WP = 5u; /* Write-Protect */
enum ulong MTRR_TYPE_WB = 6u; /* Writeback */
enum uint MSR_MTRRCAP = 0xFEu;
enum uint MSR_MTRRDEFTYPE = 0x2FFu;
enum uint MSR_MTRRPHYSBASE0 = 0x200u;
enum uint MSR_MTRRPHYSMASK0 = 0x201u;
enum ulong MTRRCAP_WC = 0x400u;
enum ulong MTRRCAP_FIX = 0x100u;
enum ulong MTRRCAP_VCNT_MASK = 0xFFu;
enum ulong MTRRDEFTYPE_E = 0x800u;
enum ulong MTRRDEFTYPE_FE = 0x400u;
enum ulong MTRRDEFTYPE_TYPE_MASK = 0xFFu;
enum ulong MTRRPHYSBASE_PHYSBASE_MASK = 0x000F_FFFF_FFFF_F000u;
enum ulong MTRRPHYSBASE_TYPE_MASK = 0xFFu;
enum ulong MTRRPHYSMASK_PHYSMASK_MASK = 0x000F_FFFF_FFFF_F000u;
enum ulong MTRRPHYSMASK_VALID = 0x800u;
struct mtrr
{
public static void initialize()
{
uint ebx;
uint ecx;
uint edx;
cpuid1(&ebx, &ecx, &edx);
if ((edx & CPUID_1_EDX_MTRR) == 0u)
{
klog.writefln("CPU does not support MTRR");
return;
}
const(ulong) mtrrcap = rdmsr(MSR_MTRRCAP);
const(ulong) mtrrdeftype = rdmsr(MSR_MTRRDEFTYPE);
}
private static ulong get_phys_base(uint n)
{
return rdmsr(MSR_MTRRPHYSBASE0 + 2u * n);
}
private static void set_phys_base(uint n, ulong physbase)
{
wrmsr(MSR_MTRRPHYSBASE0 + 2u * n, physbase);
}
private static ulong get_phys_mask(uint n)
{
return rdmsr(MSR_MTRRPHYSMASK0 + 2u * n);
}
private static void set_phys_mask(uint n, ulong physmask)
{
wrmsr(MSR_MTRRPHYSMASK0 + 2u * n, physmask);
}
}
+4 -1
View File
@@ -136,8 +136,11 @@ static assert(PageTableEntry.sizeof == 8u);
*/
struct PageTable
{
/** Number of page table entries in a page table. */
enum size_t N_ENTRIES = 512u;
/** Page table entries. */
private PageTableEntry[512] entries;
private PageTableEntry[N_ENTRIES] entries;
/**
* Access the PageTableEntry for the given address and page table level.
+42
View File
@@ -0,0 +1,42 @@
/**
* PIT (Programmable Interval Timer) functionality.
*/
module hulk.pit;
import hulk.cpu;
import hulk.klog;
struct pit
{
/** PIT input frequency in 1/1000 Hz. */
private enum ulong PIT_FREQUENCY_1000HZ = 1_193_181_667u;
private enum ulong TARGET_INTERRUPT_HZ = 100u;
private enum ulong TARGET_INTERRUPT_1000HZ = TARGET_INTERRUPT_HZ * 1000u;
private enum ulong PIT_DIVIDER = (PIT_FREQUENCY_1000HZ + TARGET_INTERRUPT_1000HZ / 2u) / TARGET_INTERRUPT_1000HZ;
/** PIT channel 0 I/O port. */
private enum ubyte PORT_CH_0 = 0x40u;
/** PIT channel 1 I/O port. */
private enum ubyte PORT_CH_1 = 0x41u;
/** PIT channel 2 I/O port. */
private enum ubyte PORT_CH_2 = 0x42u;
/** PIT mode/command register I/O port. */
private enum ubyte PORT_MC = 0x43u;
private enum ubyte MC_CH_0 = 0x00u;
private enum ubyte MC_LO_HI = 0x30u;
private enum ubyte MC_RATE_GENERATOR = 0x04u;
private enum ubyte MC_BINARY = 0x00u;
public static void initialize()
{
out8(PORT_MC, MC_CH_0 | MC_LO_HI | MC_RATE_GENERATOR | MC_BINARY);
out8(PORT_CH_0, PIT_DIVIDER & 0xFFu);
out8(PORT_CH_0, PIT_DIVIDER >> 8u);
}
public static void isr()
{
klog.writefln("PIT ISR");
}
}
+58
View File
@@ -0,0 +1,58 @@
/**
* RTC (Real-Time Clock) functionality.
*/
module hulk.rtc;
import hulk.cpu;
import hulk.klog;
import hulk.apic;
struct rtc
{
private enum ubyte PORT_SELECT = 0x70u;
private enum ubyte PORT_DATA = 0x71u;
private enum ubyte DISABLE_NMI = 0x80u;
private enum ubyte SR_A = 0xAu;
private enum ubyte SR_B = 0xBu;
private enum ubyte SR_C = 0xCu;
private enum ubyte SR_B_ENABLE_IRQ = 0x40u;
public static void initialize()
{
/* Enable IRQ 8 to receive RTC interrupts. */
out8(PORT_SELECT, DISABLE_NMI | SR_B);
ubyte sr_b = in8(PORT_DATA);
out8(PORT_SELECT, DISABLE_NMI | SR_B);
out8(PORT_DATA, sr_b | SR_B_ENABLE_IRQ);
out8(PORT_SELECT, DISABLE_NMI | SR_A);
klog.writefln("SR_A = 0x%x", in8(PORT_DATA));
/* Send EOI to enable more RTC interrupts and re-enable NMIs. */
eoi();
}
private static void eoi()
{
/* Read from status register C to clear the interrupt. */
out8(PORT_SELECT, SR_C);
in8(PORT_DATA);
}
public static void isr()
{
static __gshared ulong count;
static __gshared ulong seconds;
count++;
if ((count % 1024) == 0u)
{
seconds++;
klog.writefln("Seconds: %u", seconds);
}
eoi();
apic.eoi();
}
}
+2 -2
View File
@@ -90,7 +90,7 @@ private size_t write_hex(ulong v, bool upper, char pad, size_t width, ch_out_fn
{
static __gshared const(char)[16] hex_chars_lower = "0123456789abcdef";
static __gshared const(char)[16] hex_chars_upper = "0123456789ABCDEF";
static __gshared char[16] buf;
char[16] buf;
size_t i;
do
{
@@ -126,7 +126,7 @@ private size_t write_hex(ulong v, bool upper, char pad, size_t width, ch_out_fn
*/
private size_t write_udec(ulong v, char pad, size_t width, ch_out_fn ch_out)
{
static __gshared char[20] buf;
char[20] buf;
size_t i;
do
{